Hybrid Memory Cube nears engineering sample milestone Engineering samples of The Hybrid Memory Cube (HMC) are expected this summer, with high volume manufacturing coming next year. It will be one of the first high volume devices employing 3D integration and through silicon vias (TSVs), employing a bottom logic layer and 4-8 stacked DRAM layers. The HMC is the result of a consortium formed in late 2011 by Micron, Samsung, Altera, Xilinx and Open-Silicon to define an industry interface specification for developers, manufacturers and architects of high-performance memory technology. The consortium has grown to 110 members, including SK Hynix, IBM and ARM. Analysts are projecting the TSV-enabled 3D market to be a $40billion market by 2017, or roughly about 10% of the global chip business. We caught up with Micron’s Scott Graham, General Manager, Hybrid Memory Cube, at Semicon West. “Today, we’re very close to delivering our engineering samples this summer to our lead customers that are taking the technology into their system designs,” Graham said. The lead applications are in high performance computing, such as supercomputers, as well as the higher end networking space. “Those will be the early adopters. As we move forward in time, we’ll see that technology evolve as costs come down for TSVs and manufacturing technology, it will enter into future space where traditional DDR type of memory has resided. Beyond DDR4, we can certainly see this of memory technology being a mainstream memory,” Graham said. Since the HMC is an open specification in terms of the architecture of the device, it will be up to each memory manufacturer to decide how it might be customized and manufactured. “The way it’s done today is we source the substrate, we source the logic layer and then we bring those in-house and we complete the finishing of those logic wafers as well as all the slicing, dicing, stacking, assembly and test,” Graham said. “What we end up providing for the customer is a known good cube, or known good piece of memory, just like we would if it was a DDR device or wide I/O device,” he said. He added that the HMC is designed so that it has not only the repair capability during manufacturing but also out in the field. “It’s very flexible and very robust, so reliability is very high with this device,” he said. The consortium delivered its first specification earlier this year. “We’ve since extended the consortium to work on both future generations of the HMC technology in both the short-reach and ultra-short reach configurations,” Graham said. The HMC was designed to get high density and high bandwidth in a relatively small package. The team adopted an off-the-shelf SERDES I/O and that’s based on IBM’s 32nm process. “With that, we can achieve 10 Gbps, 12.5 Gbps, or 15 Gbps for those SERDES links,” Graham said. “If you look at a 2 GByte or a 4GByte HMC device, those first devices will deliver a total aggregate bandwidth of 160GBytes/sec. I want to emphasize those are bytes not bits. It’s a very high bandwidth and low energy per bit device that is something that can be designed into a multitude of systems.” The consortium has several generations of the HMC device planned (this summer’s engineering samples are Gen2). “As we move forward, you’ll see us moving into the 28 Gbps SERDES as far as the I/O goes,” Graham said. Bandwidths are going to be 320 Gigabytes/sec and higher, and the density will be in 4Gbyte and 8 Gbyte configurations. Graham said one of the main challenges they had to overcome was the stacking. “We’re stacking a logic layer on top of a substrate and then four to eight DRAM on top of those logic layers,” he said. “We have over 2000 TSVs in this package and it was a challenge to stack these ultrathin die and make sure that what we end up with is a high performance and very reliable package.” Graham declined to comment on the exact TSV process flow used at Micron, saying only that it was leading edge. “We had to make sure our equipment partners were up to speed and could deliver us the technology that would allow us to manufacture this in high volume,” he said. Because customer can customize the HMC design, another challenge it to make sure that the design capabilities are available at the foundry for that logic layer, Graham said. Heat dissipation in the device is achieved through a metal lid, and through the TSVs which acts as chimneys (in addition to conducting electricity). The photo shows two Gen2 HMC devices. The larger one, in a 31mm x31 mm package, is a 4 link device that will achieve 160 Gig-bytes per second. The smaller one is a two link device capable of 120 Gigabytes/sec, measuring 16mm x 19.5 mm. “Both are being manufactured now in our plant and we’re doing the whole debug phase,” explained Aron Lunde, program manager, DRAM solutions group at Micron in Boise. He said the metal lid was in contact with not only the top layer, but different internal layers. “We call it an integrated heat spreader. It makes contact at more than one level and that’s what really helps,” he said. Although manufacturers such as Micron, Samsung and SK Hynix must now handle the manufacturing, assembly and test process, Graham believes that it could eventually evolve to the point where select foundry partners would be able to provide volume manufacturing services for these HMC cubes. Graham said DDR4 will likely be the last DDR device. “Beyond DDR4, you have to move to managed memory like HMC technology,” he said. “We’re solving the memory wall problem with HMC-like architecture and what’s really going to be happening in the future is that you’ll be running into a CPU wall. That’s going to be the barrier to system progress as we move forward.” Graham expects some challenges with scaling of conventional memory at sub-20nm process nodes. “We get into physical challenges of meeting the timing requirements and the 12 pages of JEDEC specifications to be able to yield properly and to be able to provide a cost-effective memory device moving forward,” he said. Although the HMC is now designed around DRAMs, Graham said it would be possible to use other types of memories, and even a mixed set of memories. He noted Micron is looking at alternatives to the conventional DRAM cell, such as spin torque and resistive memories. “Micron is investing heavily in research in those technologies and of course the HMC team here at Micron is looking at future technologies that we can take HMC architecture and be able to utilize different DRAM or even flash types of memory,” he said. “As the technology matures and it becomes lower cost, we can see this technology certainly evolving into more global applications and utilizing different memory types in that stack – and perhaps even multiple memory types in that stack.” HMCs could eventually make their way into mobile devices, but Graham said that is likely to be three or four years away. Mobile applications presently employ low power DDR3 solutions, which will be used for several years. “We’ll see quite a few interesting designs start spinning when the mobile folks see they can differentiate with a managed memory solution. It’s not going to be HMC as we know it today, it will have to be optimized for mobile,” Graham said.