New methods to reduce time and cost of R&D SEMICON West 2013 included a robust set of technical and marketing presentations on the general theme of developing new semiconductor devices in the session “Lab to Fab: From R&D to High Volume Manufacturing” held 1:30-3:30PM on July 9. Ably moderated by Paula Doe, the session included presentations on modeling, experimenting, and prototyping new materials and structures such that they can profitably moved into high-volume manufacturing (HVM). Two of the presentations that described not just technologies but new fundamental methodologies for R&D came from Coventor and Intermolecular, small innovative companies based in Silicon Valley. Dr. David Fried, CTO of Coventor, presented how the company’s “SEMulator3D” software modeling product based on “voxels” allows for advanced physics-based modeling of unit-processes, integrated-processes, device structures, and even device electrical parameters. The modeling starts with unit-processes such as depositions, etches, and epitaxial growth at the nanometer-scale. However, unlike TCAD and other device models, this software can also extend across length scales to provide full-wafer maps of physical parameters. Fried explained how the model is built on data extracted from publicly available leading device information, such as the cross-section SEMs in Intel’s seminal IEDM paper on 22nm finFETs. The model is “behavioral” since it can predict the effects of changes in dynamic process conditions, and can therefore be used to do “virtual fabrication” of targeted devices. “You can do some interesting explorations,” explained Fried, “like what if you had a defect on a fin that was used to grow an epi-layer?” He showed how the complex interactions of different growth rates in different crystalline directions on 3D structures could be predicted by the software, and that the predicted structural shifts appear to match the SEM cross-sections shown in the literature. This modeling software can thus be used as a “virtual metrology” tool that can mimic real in-fab metrology. It can replace slow out-of-fab destructive characterization, and can provide local virtual measurements of structural parameters. It can be used to study the effects of incoming geometric parameters as well as process variations on the final structure. For example, the Cu cross-section area of a BEOL interconnect layer can be predicted, in contrast to unit-process models/controls that merely create wafer-uniformity-maps of Etch, Cu-barrier/seed PVD, Cu-ECD, Cu-CMP, and other process steps. Combinatorial R&D Dr. Raj Jammy, Sr. VP & GM Semiconductor Group, Intermolecular, Inc.—most recently a SEMATECH VP—discussed the need for new ways of doing R&D now that the integration of new materials dominates device enhancements. As semiconductor technology has evolved to smaller and smaller device geometries, the number of new materials used on CMOS chips continues to increase. Consequently, the cost of discovering and integrating new materials into complex devices structures continues to increase. New materials are needed for 3D FinFETs (alternate-channel materials), 3D Flash Memories and ReRAM (storage cells), and 3D packaging (through-silicon vias and through-mold vias), and all use complex processes with unpredictable interactions. Developing and optimizing these new materials leads to high costs for R&D and even higher costs to integrate into HVM. Intermolecular has created High Productivity Combinatorial (HPC™) tools for PVD, CVD, ALD, and wet-processing steps that allow for multiple site-isolated experiments to be done on a single 300mm wafer. When combined with throughput-match characterization tools using an automated database into what the company terms an application-specific “HPC workflow,” everything from an initial design-of-experiments (DOE) to full HVM integration can be done in 3-6 months instead of the 3-5 years needed by conventional R&D approaches. HPC workflows can accelerate R&D in the early stages of materials exploration such that an entire cycle-of-learning can occur in just 4 hours. HPC workflows can also be used with short-loop flows through a customer’s fab to allow for a 3-4 week cycle-of-learning. As an example of this methodology’s ability to accelerate learning, Jammy showed how hundreds of experimental parameters had to be explored in developing a germanium (Ge) MOS cap for CMOS integration. Variations in the substrate, surface cleaning, High-K stack, metal electrode, and post-treatment all play significant roles in determining the final device parameters. All these factors had to be co-optimized iteratively, and the project was accomplished in <3 months. IMI started in 2004 with SanDisk and ATMI, and has since added Guardian Corp., Toshiba, IBM, First Solar, GlobalFoundries, Epistar, Micron as customers.