Collaboration needed on 3D-IC

By Karen Savala, President, SEMI Americas

The history of semiconductors has been a history of collaboration.  For decades, the great leaps forward in semiconductor cost reductions and performance improvements have been achieved through widespread industry collaboration efforts in technology roadmaps, manufacturing standards, wafer size transitions, collaborative R&D consortia, international trade agreements, and other areas.  Today, a similar industry-wide collaborative approach to 3D stacked ICs is needed to reach widespread 3D-IC adoption and continue the amazing progress our industry has historically achieved.  I will be speaking on this topic at the upcoming 2013 MEPTEC Roadmaps Symposium on September 24 in Santa Clara, Calif. Here’s a preview.

In the past, when the industry was small, semiconductor progress as defined by Moore’s Law occurred nearly simultaneously in different companies.   Progress was achieved through science and technology innovation occurring through independent R&D labs and spread through academia and commercial competition.  Later, as the scale, scope and complexity of semiconductor manufacturing expanded exponentially—with much of the R&D distributed throughout the supply chain involving hundreds of equipment and materials suppliers each specializing on their unique role in the fabrication process—industry roadmaps were required to keep everyone on pace.  No single firm could master all the elements of innovation required for Moore Law improvements.  For several years it was an American effort, but in 1998 the roadmap became an international process, today’s International Technology Roadmap for Semiconductors (ITRS). Today, the ITRS has expanded to address not only critical requirements to sustain Moore’s Law, but also the key development milestones necessary in the More-Than-Moore—in areas like advanced packaging and MEMS.

Read more: Moore’s Law dead by 2022: Crying wolf?

R&D costs have also expanded to meet the targets dictated by Moore’s Law.  In the early days, only the largest R&D lab in the world, Bell Labs, could manage the multi-disciplinary requirements for semiconductor chip development.  Eventually, collaborative research consortia emerged that allowed industry players to pool resources in a pre-competitive environment to develop the science and technology needed for the next generation chip.

In addition to collaborative roadmaps and R&D, the semiconductor industry also agreed upon collective industry standards that reduced cost and spur innovation.  These standards involve such areas as wafer size and dimensions, software and hardware interfaces, materials characterization and test methods, and hundreds of other areas.  Today, there are nearly 4,000 volunteers from every major company working together on SEMI industry standards.  They have produced hundreds of widely-accepted standards that have reduced costs and allowed companies to compete on innovation. In addition to SEMI Standards, other standards bodies have emerged such as IEEE and JEDEC to address semiconductor standards needs in electrical, signaling, form factor, packaging and other areas.

Read more: New methods to reduce time and cost of R&D

With roadmaps, standards and consortia in place, the semiconductor industry targeted what was considered by some an “easy” wafer transition to 300mm silicon.  It was anything but easy. As many of you know, the transition went poorly.  The industry couldn’t agree when to introduce 300mm production and stop advanced development at 200mm, and they couldn’t afford to do both.  There were several false starts and hundreds of millions of dollars were lost.

Today, the industry is planning a 450mm wafer transition while at the same time trying to manage the increasingly complex R&D challenges of new materials development, new transistor architectures, and new packaging paradigms.  The cost of advanced semiconductor development has skyrocketed.  The industry has responded by dramatically expanding the Consortia model for collaborative R&D.

Over the last two years, the industry has launched nearly a dozen consortium-like entities in 450mm and related areas of development.  Joining Belgium’s imec, Germany’s Fraunhofer Institute, Taiwan’s ITRI, and France’s CEA-Leti—to name a few—are a number of new consortia established to collaborate on joint R&D for 450mm wafers and other next-generation semiconductor challenges.  GlobalFoundries, Intel, IBM, Samsung and TSMC formed the Global 450 Consortium (G450C) to manage 450mm wafer processing requirements. Recently, G450C set up a separate fab facility consortium.  Europe has launched five separate 450mm projects or consortiums, with two others on the drawing board. Israel has established 450mm consortium on metrology and Japan has collaborative arrangement on 450mm with Toshiba.

With uncertainties on 450 wafer processing, EUV lithography, and the continued transition to new transistor architectures, many experts are questioning the continuation of Moore’s Law.  It’s been reported that cost targets at 28 nanometers were not reached, 20 nanometers may be delayed and also come in at a high price.  Consequently, the industry has been excited about More-Than-Moore applications, especially 3D stacked ICs that promise to improve bandwidth, reduce footprint, decrease power consumption, and lower cost.

We have seen the proliferation of stacked die with wire bond or flip chip, stacked packages, package-on-package, and chip-on-chip packages. But today, the most anticipated innovation is 2.5 and 3D stacked ICs using TSVs to achieve both the power and bandwidth benefits associated with a radical new interconnect solution.

Like 450mm wafer processing, critical standards foundation work for the adoption 3D-IC is well underway.  At SEMI, Standards task forces have been established in thin wafer handling, inspection and metrology, and wafer bonding. But like 450mm wafer processing, enabling the 3D-IC revolution will require more than industry standards activities.

While a promising technology, technical challenges remain with 3D stacked ICs.  Many companies have a silicon interposer or 2.5D solution on their packaging roadmaps where a logic device is mounted next to a stack of memory and the TSVs are in the substrate.  However, while Samsung and others have made announcements, affordable stacked memory is not yet available.  In addition, many companies are also looking at alternatives to silicon interposers, such as glass interposers, to bring the price down.  So, even 2.5D has been delayed and questions remain about its configuration at high volume.  For heterogeneous integration of memory and logic, the industry still needs design tools, thermal solutions, continued work on wafer bonding and de-bonding, and accepted test methodologies, to name a few requirements.

Gartner estimates that TSV adoption for memory will be pushed out to 2014 or 2015, with non-memory applications delayed to 2016-17 if that. They currently forecast that TSV devices will account for less five percent of the units in the total wafer-level packaging market by 2017.

For 3D-IC to be widely adopted, meaningful collaboration throughout the value chain still needs to occur.  At this time in the market, all the important players in the ecosystem have a different perspective.  All the players have a business model that must be defended or exploited based on what technical discoveries occur and what customers eventually want. TSMC sees an integrated approach that threatens the traditional Fabless/Foundry/OSAT model.  Obviously leading OSATs prefer this vision as it provides an opportunity to expand their business.  But OSATs themselves are looking at ways to differentiate.  IDMs like Intel probably see the fabless model coming full circle with 3D IC. Fabless companies believe that 3D must emerge in ways that continue their own—and their customer’s — familiar multiple-sourcing considerations.

We’ll continue to see discoveries, inventions and new products in 3D-IC and progress will continue.  Hundreds of patents in the area have already been issued.  We’re seeing innovation and invention in wafer bonding, via manufacturing, and other areas.  Standards work at JEDEC and SEMI will also contribute to the market’s development, both to enable processes and cost-reduce manufacturing, but without the emergence of a new, robust collaboration model that can deliver meaningful agreements between key constituencies, the promise of 3D innovation will remain distant and illusive.

In addition to 2013 MEPTEC Roadmaps Symposium (September 24), 3D-IC industry progress will also be the subject of the SIP Global Summit (September 5-6) held in conjunction with SEMICON Taiwan, and The Advanced Packaging Conference  (October 8-9) at SEMICON Eu

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