By Ron Press, Mentor Graphics Corp
Scan testing is the standard practice for test of integrated circuits. The vast majority of IC production test is based on automatic test pattern generation (ATPG) using the scan logic. Scan ATPG is a mature technology with very predictable and high quality results. It also enables precise defect diagnosis to help yield analysis and improvement. With the growth in the size of ICs and smaller fabrication processes, embedded compression was added to the scan DFT logic, which reduces the growing time to apply tests by a couple of orders of magnitude. Today, embedded compression is commonplace.
However, some devices must be tested when there is little or no tester interface available. In these cases, built-in self-test (BIST) is necessary. Recently, the growth in ICs for safety critical applications, like automotive and medical, has boosted the demand for BIST. However, more and more ICs need both kinds of test. It turns out that embedded compression and logic BIST use similar types of logic, so it makes sense to save DFT logic area by sharing the compression and BIST logic in a hybrid test solution. The DFT and infrastructure of each technology can also provide advantages to the other technology. This kind of hybrid compression/BIST solution not only saves DFT area, but provides better test quality.
With the hybrid test approach, you have the option to provide embedded compression ATPG patterns from a tester or to have the patterns automatically applied and analyzed within the device logic BIST. You can insert hybrid logic in a top-down flow with a central controller and shared compression decompressor/LFSR and compaction/MISR logic in one or more blocks (Fig 1). You can also do it in a bottom-up flow, which lets you complete the logic insertion in each block, including wrapper isolation chains. The resulting blocks with hybrid test logic can be used in any IC and the logic BIST or embedded compression patterns for the block can be directly retargeted. This plug-n-play logic and pattern approach saves significant ATPG time in the top-level IC.
Embedded compression ATPG provides advantages to logic BIST in a hybrid solution. Because embedded compression ATPG has high quality production defect detection, the logic BIST might not be required to have as high a fault detection. Thus, fewer test points are necessary for random pattern resistive logic, which could be a significant logic BIST area savings. Another advantage that originally came from embedded compression is low power test. The hybrid test approach uses low power shift logic so that the toggle activity can be selected by the user in either ATPG or BIST.
Similarly, logic BIST in a hybrid approach provides advantages for embedded compression ATPG. X-bounding used by logic BIST to remove unknown states is necessary to produce a predictable signature in the MISR. It also makes the circuit much more testable for ATPG, especially if any test points are also added. As a result, the logic BIST infrastructure provided in the hybrid approach causes embedded compression ATPG to have higher coverage and fewer patterns. ATPG is normally the primary means of defect detection, but with logic BIST additional detection is possible due to the high number of detections of each fault (high multiple detection).
These are all compelling reasons why a hybrid test approach is attractive for any user implementing logic BIST. In fact, it is being adopted by automotive IC designers who need both autonomous test and very high-quality production ATPG patterns. What many don’t realize is that it also provides notable advantages for ATPG even if a hard logic BIST requirement doesn’t exist. With this approach, burn-in doesn’t need a tester to apply ATPG patterns since logic BIST could be used and overall ATPG compression and pattern count are improved.
Figure 1. A hybrid test solution with compression (embedded deterministic test) and logic BIST sharing a majority of the decompressor/LFSR and compactor/MSIR logic.
Ron Press is the technical marketing manager of the Silicon Test Solutions products at Mentor Graphics. The 25-year veteran of the test and DFT (design-for-test) industry has presented seminars on DFT and test throughout the world. He has published dozens of papers in the field of test, is a member of the International Test Conference (ITC) Steering Committee, and is a Golden Core member of the IEEE Computer Society, and a Senior Member of IEEE. Press has patents on reduced-pin-count testing and glitch-free clock switching.