IBM develops sub-20nm nanofluidic channels for lab-on-chip

Nanofluidic channels are useful for many biological and chemical applications, such as DNA sequencing, drug delivery, blood cell sorting and molecular sensing and detection. But in the effort to build a versatile lab-on-a-chip, it has been challenging to develop a wafer-scale nanochannel fabrication process compatible with CMOS technology.

At the upcoming International Electron Devices Meeting (IEDM), to be held December 9-11 in Washington, D.C., IBM researchers will report on a CMOS-compatible 200 mm wafer-scale sub-20nm nanochannel fabrication method that enables stretching, translocation and real-time fluorescence microscopy imaging of single DNA molecules.

Through the use of sacrificial XeF2 etching and various UV and e-beam lithography methods, sub-20-nm patterns in silicon were converted into macro-scale fluidic ports, micro-scale fluidic feed channels, and nano-scale channels for DNA imaging. Gradient nanopillars were located in the channels to stretch DNA molecules prior to imaging them. Fluid wasn’t pumped through the channels, but instead was transported by the force of gravity. The researchers say their techniques lead to highly manufacturable structures and can produce chips for a variety of biological applications.

A schematic of the nanochannel architecture. Grey represents silicon layers, while blue represents SiO2.  The silicon layers serve as sacrificial material.

A schematic of the nanochannel architecture. Grey represents silicon layers, while blue represents SiO2. The silicon layers serve as sacrificial material.

The etching sequence of the silicon layers is shown: A) silicon-patterning with sub-20 nm features (note the inset SEM electron microscope photo); B) capping-oxide deposition followed by vent-hole patterning: and C) XeF2 gas-phase etching of silicon patterns embedded in SiO2.

The etching sequence of the silicon layers is shown: A) silicon-patterning with sub-20 nm features (note the inset SEM electron microscope photo); B) capping-oxide deposition followed by vent-hole patterning: and C) XeF2 gas-phase etching of silicon patterns embedded in SiO2.

SEM electron microscope photo of silicon nanochannels.

SEM electron microscope photo of silicon nanochannels.

Optical photos showing A,B) nanochannels with vent holes on 1-2 µm SiO2 capping layer, on top of silicon patterns; and C,D) following gas etching and removal of silicon patterns.

Optical photos showing A,B) nanochannels with vent holes on 1-2 µm SiO2 capping layer, on top of silicon patterns; and C,D) following gas etching and removal of silicon patterns.

Wang (14.1) Fig.12 (450x338)

 

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