By Tom Morrow, chief marketing officer, SEMI
While the number of materials used in semiconductor logic will increase approximately 50 percent in the transition from 32nm to 22nm production, the materials revolution in memory will be even more pronounced, challenging developers, manufacturers, equipment, and materials suppliers, according to experts speaking at the SEMI Strategic Materials Conference 2013, held in Santa Clara on October 16-17. The revolution is being sparked by immediate challenges in DRAM, NAND, 3D and embedded memory at 20nm, and possible scaling limitation of that NAND and NOR flash memory beyond 20 nm. Beyond that node, the industry is looking at new nonvolatile memory structures such as PCRAM, ReRAM, STT-RAM with novel material-sets targeted for high-volume production by 2015-2017. Further out, magnetic tunneling devices and nanoscale multiferroics may be emerging faster than you think.
“You are going to see an explosion of materials in memory,” said Gregg Bartlett, senior VP and CTO of GLOBALFOUNDRIES, closing the two-day SMC. Bartlett also noted that materials were eclipsing equipment as the largest cost contributor.
One area of immediate and comprehensive change is addressing the scaling and performance challenges of 3D stacked memories. Michel Koopmans, packaging integration manager at Micron, discussed Micron’s 3D stacked DRAM roadmap and the key challenges currently being addressed in R&D and process development. Micron is currently providing samples of a substrate-based TSV and 3D stacked hybrid memory cube. The HMC Gen 2 product offers the bandwidth (160 GB/s) power (6-8 pJ/bit) and density specifications (2GB & 4GB) that can only be achieved with TVS 3DI solutions, but Micron’s goal is to eliminate the laminate based substrates to further reduce packaging material cost, form factor and power requirements. According to Koopmans, new technologies are being developed to overcome various wafer level and package level manufacturing challenges and introduce all silicon cubes. From silicon interposers to known good stacked devices in an all silicon form factor, enabling future packaging solutions will require improved and revolutionary materials.
Manufacturing challenges for all silicon cubes include the need for new processes and assembly technologies, but also for new materials. Koopmans outlined detailed material requirements for TSV liners, TSV seed/barriers, plating chemistries, bump/pillars photo resists, carrier adhesives, backside dielectrics, and wafer level underfill needed for future generations of 3D memory. Besides modified wafer level encapsulation techniques, protecting the all silicon cube may also require new technologies such as spin-on epoxy’s or conformal films. Enabling this new future, will also require a new level of collaboration between fabs, design and assembly operations.
Unlike the recent past, memory manufacturers today are increasingly on highly divergent development paths with highly specialized materials requirements and process implications. Er-Xuan Ping, Ph.D. and managing director at Applied Material’s Silicon Systems Group, also presented at the Strategic Material Conference. Dr. Ping sees materials innovation and associated process developments accelerating for both current and new memory technologies. In NAND scaling, sub 40nm technologies including silicon-oxide-nitride-oxide-silicon (SONOS), TANOS (TaN-Al2O 3-nitride-oxide- silicon) and MONOS (metal-ONOS) structures are all in development. SRAM transistors are migrating mobility channel solutions from Si to SiGe, Ge, and III-V, contact technologies from NiPtSi, to TiSi and MIS, and backend of line technologies from Cu to Ru. Embedded flash is moving to low temperature processing and high K metal gates to meet immediate scaling challenges. Future embedded NVM may utilize submicron nano dots to achieve floating gate operations at required densities and performance.
The dramatic changes in memory technology may be just around the corner. Non-charge based memories, such as phase change memory (PCRAM), spin-transfer torque switching (STT-RAM) and resistive random-access memory (RRAM or ReRAM) are in early adoption with enormous challenges in material and process improvement required to enable high volume manufacturing. Dr. Ping discussed ReRAM improvement paths include top electrode materials, MeOX modification and MeOX stack; PC RAM current reduction developments using materials modification, thermal efficiency and reduced volumes; and STT RAM low current paths including dual and perpendicular magnetic tunnel junctions (MTJs), among other topics, and their unique process requirements in ALD, PVD, and RIE, IBE processing.
The recognition that scaling limitations are fast approaching has created heightened interest in beyond-CMOS technologies. Stuart Parkin, Ph.D. and IBM Fellow at IBM’s Almaden Research Center discussed the latest developments in using atomically engineered magnetic heterostructures to create spin-polarized electron currents in new devices typically referred to as spintronics. He discussed a new Racetrack Memory concept utilizing novel three dimensional technology to store information as a series of magnetic domain walls in nanowires, manipulated by spin polarized currents. Spintronic devices may even allow for “plastic” devices that mimic synaptic switches in the brain, thereby allowing for the possibility of very low power computing devices.
In another long-term possibility, professor Greg P. Carman, Ph.D., director of translational applications of multiferroic systems at UCLA, described recent discoveries that suggest that a ferromagnetic material’s intrinsic magnetization can be manipulated with an electric field, enabling new memory, antenna and motor devices. One multiferroic approach relies on mechanically coupling a single crystal piezoelectric material to a magnetostrictive material where an electric field induces a strain to reorient the material’s magnetization state. Using physical phenomenon present in nanoscale magnetic elements significantly enhances the electric field induced magnetic changes with efficiencies that could approach 60 percent.
The two-day SEMI Strategic Materials Conference offered presentations from leading market analysts, leading manufacturers, industry consortiums, top suppliers and academic researchers, along with an innovative interactive format designed to facilitate business contacts and networking. In addition to these insights into memory developments, SMC also provided forecasting information and R&D insights from the materials perspective on logic, carbon-based materials, MEMs, and printed/organic electronics. This multi-market perspective allows the annual SMC to uncover technology synergies and business cross over opportunities among various materials-enabled devices and industries. This year’s keynotes were provided by Gregg Bartlett, senior VP and CTO, GLOBALFOUNDRIES, and Jo de Boeck, Ph.D., senior VP and CTO, imec. For information on SEMI, visit www.semi.org.