An alternative to scaling is to expand vertically, by thinning, stacking and interconnecting ICs, commonly called 3D integration. Chip-to-chip Interconnections are are typically made with through-silicon vias (TSVs), but some TSVs also have major disadvantages, including relatively large dimensions, parasitic capacitances and thermal mismatch issues.
At the upcoming International Electron Devices Meeting (IEDM) in December, researchers from Taiwan’s National Nano Device Laboratories avoided the use of TSVs by fabricating a monolithic sub-50nm 3D chip, which integrates high-speed logic and nonvolatile and SRAM memories. They built it from ultrathin-body MOSFETs isolated by 300-nm-thick interlayer dielectric layers.
To build the device layers, the researchers deposited amorphous silicon and crystallized it with laser pulses. They then used a novel low-temperature chemical mechanical planarization (CMP) technique to thin and planarize the silicon, enabling the fabrication of ultrathin, ultraflat devices. The monolithic 3D architecture demonstrated high performance – 3-ps logic circuits, 1-T 500ns nonvolatile memories and 6T SRAMs with low noise and small footprints, making it potentially suitable for compact, energy-efficient mobile products.