TSMC to unveil 16nm FinFET platform at IEDM

At the International Electron Devices Meeting (IEDM) in December, TSMC researchers will unveil a 16nm FinFET process that by many measures is one of the world’s most advanced semiconductor technologies.

 

In size, it is the first integrated technology platform to be announced below the 20 nm node, with key features including a 48-nm fin  pitch and the smallest SRAM ever incorporated into an integrated process—a 128-Mb SRAM measuring 0.07 µm2 per bit. In performance, it demonstrated either a 35% speed gain or a 55% power reduction over TSMC’s existing 28-nm high-k/metal gate planar process, itself a highly advanced technology, and had twice the transistor density.  Short-channel effects were well-controlled, with DIBL <30 mV/V, saturation current of 520/525 µA/µm at 0.75V (NMOS and PMOS, respectively) and off-current of 30 pA/µm. It incorporates seven levels of high-density copper/low k interconnect and high-density planar MIM devices for noise control.

Figure 1 shows that the 16 nm FinFET achieved either a >35% speed gain or >55% power reduction over TSMC’s planar process.

Figure 1 shows that the 16 nm FinFET achieved either a >35% speed gain or >55% power reduction over TSMC’s planar process.

 

Figure 2 shows a cross-section of the device’s 7-level metal copper/low-k architecture.

Figure 2 shows a cross-section of the device’s 7-level metal copper/low-k architecture.

 

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