GLOBALFOUNDRIES demonstrates model for next-generation chip packaging technologies

GLOBALFOUNDRIES today unveiled details of a project that demonstrates the value of its open and collaborative approach to delivering next-generation chip packaging technologies. The company, in partnership with Open-Silicon (chief architect) and Amkor Technology, Inc. (assembly and test), jointly exhibited a functional system-on-chip (SoC) solution featuring two 28nm logic chips, with embedded ARM processors, connected across a 2.5D silicon interposer. The jointly developed design is a test vehicle that showcases the benefits of 2.5D technology for mobile and low-power server applications and the viability of the Foundry 2.0 collaborative enablement model.

While some semiconductor manufacturers are approaching next-generation packaging technologies through internal development, GLOBALFOUNDRIES is enabling an open supply chain through collaboration with ecosystem partners and customers. This approach allows GLOBALFOUNDRIES’ customers to choose their preferred supply chain partners, while leveraging the experience of ecosystem partners who have developed deep expertise in design, assembly and test methodologies. When combined with GLOBALFOUNDRIES’ leading-edge manufacturing capabilities, this open and collaborative model is expected to deliver lower overall cost and less risk in bringing 2.5D technologies to market.

“As the fabless-foundry business model evolves to address the realities of today’s dynamic market, foundries are taking on increasing responsibility for enabling the supply chain to deliver end-to-end solutions that meet the requirements of the broad range of leading-edge designs,” said David McCann, vice president of packaging R&D at GLOBALFOUNDRIES. “To help address these challenges, we are driving our ‘Foundry 2.0’ collaborative supply chain model by engaging early with ecosystem partners like Open-Silicon and Amkor to jointly develop solutions that will enable the next wave of innovation in the industry.”

The test vehicle features two ARM Cortex-A9 processors manufactured using GLOBALFOUNDRIES’ 28nm-SLP (Super Low Power) process technology. The processors are attached to a silicon interposer, which is built on a 65nm manufacturing flow with through-silicon-vias (TSVs) to enable high-bandwidth communication between the chips.

Open-Silicon provided the processor, interposer, substrate, and test design, as well as the test and characterization of the final product. GLOBALFOUNDRIES provided the PDKs, interposer reference flow and manufactured both the 28nm ARM processors and the 65nm silicon interposer with embedded TSVs. Amkor provided the package-related design rules and manufacturing processes for back-side integration, copper pillar micro-bumping, and 2.5D product assembly. GLOBALFOUNDRIES and Amkor collaborated closely throughout the project to develop and validate the design rules, assembly processes, and required material sets.

The companies demonstrated first-time functionality of the processor, interposer, and substrate designs, and the die-to-substrate (D2S) process used by the supply chain resulted in high yields. The design tools, process design kit (PDK), design rules, and supply chain are now in place and proven for 2.5D interposer products from GLOBALFOUNDRIES, Amkor, and Open-Silicon.

“This project is a testament to the value of an open and collaborative approach to innovation, leveraging expertise from across the supply chain to demonstrate progress in bringing a critical enabling technology to market,” said Ron Huemoeller, senior vice president of advanced product development at Amkor Technology. “This collaborative model will offer chip designers a flexible approach to 2.5D SoC designs, while delivering cost savings, faster time-to-volume, and a reduction in the technical risk associated with developing new technologies.”

“We are pleased to be at the forefront of making 2.5D a reality with our foundry and OSAT partners,” said Dr. Shafy Eltoukhy, vice president of technology development at Open-Silicon. “This approach will allow designers to choose the right technology for each function of their SoC while simultaneously enabling finer grain and lower power connectivity than traditional packaging solutions along with reduced power budgets for next-generation electronic devices.”

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