Consistent equipment performance, avoiding unscheduled downtime, reducing defects and preventing excursions is key to reducing cost and improving die and line yield in semiconductor manufacturing. The fully automated InnerSense SmartWafer (SMW2) system addresses these key metrics. The SMW2 system is effectively being used as a predictive monitor for handler PM’s, a leading indicator for mechanical defects and can detect, predict and prevent most mechanical related excursions, including wafer damage that can lead to subsequent wafer breakage. The SMW2 system can further improve tool availability by improving post PM recovery and tool matching.January 24, 2017 Sponsored by InnerSense
The upcoming IEEE 802.11ax High-Efficiency Wireless (HEW) standard promises to deliver four times greater data throughput per user. It relies on multiuser technologies to make better use of the available Wi-Fi channels and serve more devices in dense user environments. Explore this technology introduction white paper to learn about the new applications of 802.11ax, the key technical innovations to the standard, and its test and measurement challenges. January 10, 2017 Sponsored by National Instruments
Continued scaling and more complex device structures, including FinFETs and 3D stacking, are creating new challenges in metrology and inspection. Smaller defects must be detected and analyzed on an increasingly diverse set of materials. Chip makers are looking for better wafer edge inspection techniques, higher resolution metrology tools and new compositional analysis solutions. Experts will describe new approaches for next generation metrology and inspection, including measurements of CDs, stress, film thickness and non-visual defects.
Back-end packaging is increasingly important to semiconductor device form factor, thermal and power performance, and costs. Compounded by the demand for lead-free processing and the soaring cost of gold, the industry is developing new approaches to packaging, including redistribution layers (RDL), through silicon vias (TSV), copper pillars, wafer-level packaging (WLP) and copper wire bonding. Experts will discuss these and other approaches in this webcast.