By Dr. Phil Garrou – Contributing Editor
3DIC memory, and therefore all of 2.5/3D technology, took one step closer to full commercialization last week with the HBM joint development announcement from AMD and Hynix at the RTI 3D ASIP meeting in Burlingame CA.
Bryan Black, Sr Fellow and 3D program manager at AMD noted that while die stacking has caught on in FPGAs and image sensors “..there is nothing yet in mainstream computing CPUs, GPUs or APUs” but that “HBM (high bandwidth memory) will change this.” Black continued, “Getting 3D going will take a BOLD move and AMD is ready to make that move.” Black announced that AMD is co-developing HBM with SK Hynix which is currently sampling the HBM memory stacks and that AMD “…is ready to work with customers.”
Minsuk Suh, principle engineer at Hynix confirmed that they are reading both 3D stacked memory for main memory and 3D stacked HBM for networking and graphics applications. JEDEC specifications for these products are “mostly finalized.”
Suh indicated that the first application for HBM would be GPUs and that it will next move to networking and HPC applications. Initial details on the HBM processing sequence show a standard vias middle /carrier bonding / thin and via reveal / backside process / stack . TSV are on 40 micron pitch. HBM stacks show a 30% power reduction and a 37X size reduction over standard DDR4.
More details coming in future IFTLE blogs…