Microelectromechanical systems (MEMS) present both unique market opportunities and significant manufacturing challenges for product designers in nearly every application segment. Used as accelerometers, pressure sensors, optical devices, microfluidic devices, and more, these microfabricated sensors and actuators often need to be exposed to the environment, but also need to be protected from environmental factors. Although standard semiconductor manufacturing methods provide a baseline capability in meeting these challenges, the unique requirements of MEMS devices drive a need for specialized epoxies and adhesives able to satisfy often-conflicting demands.May 12, 2016 Sponsored by Master Bond, Inc.,
This whitepaper provides a comprehensive overview of parylene conformal
coating, advantages of parylene, and applications for parylene to
protect electronic devices.
As technology continues to advance, devices will encounter rugged
environments and it is vital that they are properly protected. Parylene
conformal coating is one way that manufacturers are giving their devices
a higher level of protection, along with increasing the overall quality
of their products.
Parylene conformal coating applications for Electronics include:
· I/O & PCI Modules
· Power Converters and Supplies
· Other Embedded Computing applications
· Other specialty electronics and assemblies April 26, 2016 Sponsored by Diamond-MT
May 26, 2016 at 1 PM ET / Sponsored by Zeta Instruments
Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging. Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market. In this webcast, industry experts will explain the FOWLP process, discuss recent advances and forecast future trends.
June 21, 2016 at 1 PM ET / Sponsored by Air Products
Transistor performance has been greatly improved with strained silicon and high-k metal gates. Further performance improvements could be had by implementing III-V materials in the channel of nMOS transistors. Both III-V and Ge-based channels being considered for the pMOS device. High electron-mobility III-V semiconductors have been intensely researched as alternative channel materials for sub-7 nm technology nodes, but one of the main stumbling blocks is how to integrate them monolithically and cost-effectively with traditional CMOS silicon technology. This webcast will discuss the latest efforts in this area, including vertically stacked III-V nanowire.