FinFET evolution for the 7nm and 5nm CMOS technology nodes AARON THEAN, imec, Leuven, Belgium In addition to extending the fin-based design investments, augmenting the FinFET for improved performance allows an evolution of the process infrastructure for a few more nodes. With 14nm CMOS technology node soon to be ready for production and the leaders in the industry busy with 10nm development, our R&D focus shifts to scaling devices for the 7nm and 5nm technology nodes. In the post-planar transistor era, chip power continues to be a major challenge and the need for low-voltage transistors is ever more important. With a goal to reduce close to 50% of the supply voltage (Vdd<0.5-0.6V) relative to today’s most advanced microprocessors in production, significant improvements of transistor short-channel electrostatics as well as performance are sought. It remains hard to tolerate a lackluster performance with density scaling, especially when process cost rises significantly. Figure 1: Sub-threshold Swing (S) of a MOSFET. “Souping-up” the FinFET is the order of the day. Besides extending the fin-based design investments, augmenting the FinFET for improved performance allows us to gently evolve the process infrastructure for a few more nodes. However, to do better than today’s FinFET performance is no easy feat. Just to maintain the sub-threshold swing close to ideal (65 mV/dec-70 mV/dec), a measure of transistor switching quality (important for low Vdd) (FIGURE 1), fin thicknesses have to be scaled to 7nm or thinner, for gate length of 20nm and 15nm, targeted for 7nm and 5nm, respectively (FIGURE 2). The new paradigm is here, where we have a transistor feature (fin) that needs to be patterned more aggressively than the gate length, while rivaling the device’s high-k gate dielectric (typically~2nm), already in the order of 4 atomic lattices. Moreover, the aggressively-tight gate pitch (~40-48nm by 7nm node) and tiny device volume make doping, and strain engineering for performance very tricky. Figure 2: Cross-sectional TEM Images of Si FinFET targeting 10nm CMOS. Fortunately, we are not at the end of the road yet, and there are options. The first is to extend good-old silicon channel, by focusing on improving electrostatics, leakage isolation issues and strain engineering. Options like gate-all-around (nanowires), steep retrograde wells (ground planes), and Si:C/Ge stressors are being investigated. We reach for a new bag of tricks as well. Why not replace the Si channel by non-Si high-mobility materials? I mean literally etch out Si and epitaxially re-grow non-Si materials of desired properties. Several desired high mobility materials are being considered because the effectiveness of conventional stressors, like source/drain stressors, strongly reduces when transistors shrink. We also investigate SiGe, Ge and III-V replacement fin process (FIGURE 3). Figure 3: Cross-sectional TEM images Left: SiGe on Si Fins, Middle: strained Ge/SiGe on Si, Right: InGaAs/InP on Si Fins. The learning curve to master these materials (for FinFETs) is steep. For example, introducing Ge into a fin is not a trivial process when it agglomerates easily with higher process temperatures. On the device side, leakages due to narrow band gap, gate-stack passivation, and defectivitiy are on-going hurdles. Moreover, any technique employed to integrate Ge in the pFET must be CMOS compatible, which means that it must allow a co-integration with materials for nFETS, like Si, III-V materials. For all these challenging options, it is our goal to identify, for our technology partners, the promising options, innovate on the solutions, and work-out the design/system impact. Recent work on novel devices that have Ge as a pFET channel material (6x gain in mobility wrt Si) in combination with III-V materials like InGaAs for nFETs, has turned out very promising. For the Ge-channel based pFET, strain boosting technologies are mandatory in order to outperform the conventional strained Si FinFET devices. Imec researchers have found a way to implement strain on Ge pMOS devices by using a Si1-xGex strain relaxed buffer (SRB) that epitaxially-replaced Si. The epitaxial buffer not only helps reducing the mismatch in atomic spacing, it also provides a way of introducing strain in the Ge layer. Besides being an efficient stressor, additional electrostatic benefit arises from the Ge/SiGe quantum well confinement. Some major optimizations in terms of doping and passivation allowed us to achieve good performance characteristics, as will be shown at the upcoming IEDM conference. The co-integration of this first strained Ge-based pFET device with alternative nMOS channel materials however still comes with major integration challenges. Obviously, there is still much work to do. Also, it has become clear that scaling the transistor into the 7nm and 5nm nodes is no longer ‘business as usual’. But looking back at the last ten years, CMOS scaling hasn’t been usual either, while still enabling good business. Since the days we replaced Si source-drain with embedded SiGe stressors, we are working our way towards heterogeneous material integration. Exciting possibilities for CMOS and beyond are ahead of us and we need to make it happen through early collaboration on various aspects of the technology: materials, tools, patterning and process integration. Now, we just need to figure our way out of that pesky variability issue. • AARON THEAN , is the Director of the Logic Device Program at imec, Leuven, Belgium.