Substrate impact on 2.5/3D IC costs

Dr. Phil Garrou, Contributing Editor

At the recent Georgia Tech Global Interposer Technology (GIT) Workshop in Atlanta, the pervasive theme appeared to be whether a change in substrate is required to lower overall costs and help drive HVM (high volume manufacturing) applications. Certainly conference chair Rao Tummala, industry visionary whose name is synonomous with microelectronic packaging, feels the time is right to take a serious look at glass interposers both for their superior electrical performance and their promise of lower costs. The PB substrate manufacturers are also taking a serious look at this market and proposing that they can drive their technology to the required dimensions and electrical performance, though many skeptics (including me) are taking a “show me” attitude about these claims.

The Yole Developpement presentation pointed out that while 2.5D silicon interposer technology was fully underway at TSMC and GLOBALFOUNDRIES, UMC and SPIL supposedly are near initiation, all of the rumored “driver applications,” like the Apple A7, the next gen Qualcomm phone, the Sony PS4, ST Micro’s “Wioming” application processor, wide IO memory and the next generation Altera FPGA (see discussion below) have been, at the very least, postponed. While no one would openly reveal what the current and proposed future costs are, it is believed that all of these postponements are due to cost which certainly is not yet meeting the mobile phone requirements of less than 1 cent per sq mm proposed by Qualcomm’s Matt Nowak (i.e., this is roughly $550 for a 300mm wafer of interposers).

While Yole has identified at least 10 products moving towards commercialization, all of them currently require so called high density interposers (i.e. 1 µ m L/S and as small as 10 µ m TSV). Currently these dimensions can only be fabricated using front end dual damascene type processing available only at silicon foundries and more recently the OSAT, SPIL.

While Yole is still projecting a greater than $1B in revenue from 2.5D TSV activity by 2017 (activity revenues including TSV etching, filling, RDL, bumping, wafer test & wafer level assembly), these projections only hold if the current “postponed applications” are quickly commercialized.

During the Amkor presentation Ron Huemoeller indicated that lowering cost could come from elimination of backside RDL on the interposers by arranging pin out on the top side high density interconnect.

Huemoeller sees high end applications being dominated by silicon, mid end applications like graphics possibly using glass and the low end applications (yet unidentified) being wide open. He sees GPU + HBM (high bandwidth memory) being adopted in 2015 and tablets and processors adopting interposer solutions the following year.

In terms of organic “interposers” he indicates that Shinko and Semco are in limited sampling of 2/2 (L/S) and Kyocera 5/5. He labels Unimicron as in “early development.”

After making the standard argument that 2.5/3DIC was needed to combat the costs of continued scaling and that system level cost savings could pay for interposer costs, Dave McCann of GLOBALFOUNDRIES indicated that GF was achieving near 100% yields with reticle sized interposers having 4 layers of high density interconnect.

McCann predicted we would see voltage regulator function on future interposers. He also described a program between Global (chip and silicon interposer), Open-Silicon (design), Cadence (EDA tools) and Amkor (assembly and test), which produced a functional processor vehicle featuring two 28nm ARM Cortex-A9 processors connected on a 2.5D silicon interposer built on a 65nm manufacturing flow. The program demonstrated first-time functionality of the processor, interposer, substrate and the die-to-substrate assembly process. The design tools, process design kit (PDK), design rules, and supply chain are now in place for other activities.

Inherently most believe that all things being equal, glass should be a lower cost interposer solution since it can be processed in large format. However, one interesting question from the audience was “Why are silicon and glass wafer the same price?”

Although the data from experts like Professor Kim from KAIST confirms that glass is a better electrical performance solution, especially for RF applications, the major issue is that a complete infrastructure is not yet in place to manufacture such glass interposers. •

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <strike> <strong>

NEW PRODUCTS

Entegris announces GateKeeper GPS platform
07/15/2014Entegris, Inc., announced last week the launch of GateKeeper GPS, its next-generation of automated regeneration gas purification system (GPS) technology....
Bruker introduces Inspire nanoscale chemical mapping system
07/15/2014Bruker today announced the release of Inspire, the first integrated scanning probe microscopy (SPM) infrared system for 10-nanometer spatial...
MEMS wafer inspection system from Sonoscan
06/25/2014Sonoscan has announced its AW322 200 fully automated system for ultrasonic inspection of MEMS wafers....