By Zhihong Liu, Executive Chairman, ProPlus Design Solutions, Inc., San Jose, Calif.
FinFET technology, with its multi-gate architecture for superior scalability, is gaining momentum with foundries, EDA vendors and fabless design companies, a welcome trend that began in 2013 and will continue into 2014.
Enormous effort has been expended already by leading manufactures such as GLOBALFOUNDRIES, Intel, Samsung and TSMC and their EDA partners to support the new technology node that offers so much promise. The move to FinFET portends good things for the semiconductor industry as it enables continuous Moore’s Law scaling down to sub-10nm and delivers higher performance and lower power consumptions. The revolutionary device architecture also brings challenges to designers and EDA companies developing FinFET design tools and methodologies. The achievement of FinFET solution readiness across the design flow is a significant accomplishment, especially considering the PDK itself was migrating in parallel from v0.1 and v0.5 toward v1.0.
The industry-standard BSIM-CMG model, developed by the BSIM group at the University of California at Berkeley, uses complicated surface-potential based equations to model FinFET devices, which also require complex parasitic resistance and capacitance models. As a result, SPICE simulation performance is known to be a few times slower than bulk technology with BSIM4 models. In addition, netlist sizes for FinFET designs are large, especially for post-layout extracted simulations, the norm given the impact of process variations, including layout effects on a design. Lower Vdd, increased parasitic capacitance coupling and noise sensitivity create a need for high accuracy circuit SPICE simulation where convergence of currents and charges is carefully controlled. These issues significantly impact the type of circuit simulation solution that will be viable for FinFETs.
FinFET poses many other design challenges that both EDA vendors and designers have to respond to. For example, “width quantization” puts new requirements on analog and standard cell designers. They can only use quantized widths instead of arbitrary width values in their designs.
The FinFET harvest is just beginning. As production tapeout activity ramps up, more emphasis will be placed on improving the performance of design flows, such as accelerating simulation and better sampling methods for corners or high sigma Monte Carlo analysis. Parametric yield will continue to be a key requirement as design houses attempt to maximize ROI from an existing node or to maximize the investment into a new node. The days of “margining” to safeguard a design are over. At the newer nodes, designers will invest more time figuring out where the yield cliff actually is and making sure their design is robust and will yield in production.
As a result, designers will have to seek out new tools and methodologies to overcome FinFET design challenges. One example is the adoption of giga-scale parallel SPICE simulators to harness circuit simulation challenges in FinFET designs. Traditional SPICE simulators don’t have the capacity and lack sufficient performance to support FinFET designs, while FastSPICE simulators likely will not meet accuracy requirements. Another example is where FinFETs have created increased interest in high sigma analysis of library designs such as SRAMs, standard cells and I/Os. Designers are working hard to fulfill a foundry requirement to verify bitcell designs to 7 sigma. That requirement can only be achieved by proven variation analysis tools that can support large capacity and high sigma yield analysis out to high sigma values.
Yes, FinFET could be the technology to give the semiconductor and EDA industry a major boost. I say long live FinFET.
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