Cadence PVS certified for GlobalFoundries’ 65nm to 14nm processes

Cadence Design Systems, Inc. announced today that GLOBALFOUNDRIES certified the Cadence Physical Verification System (PVS) for custom/analog, digital and mixed-signal design physical signoff for 65nm to 14nm FinFET process technologies. The certification covers Cadence-qualified PVS rule decks for physical verification used in Cadence Virtuoso Integrated Physical Verification System, Cadence Encounter Digital Implementation System and full-chip signoff. Certified Cadence PVS rule decks are essential for mutual customers to fully leverage in-design physical verification in Cadence analog and digital flows, and to complete full-chip physical signoff.

“As innovators move to these smaller geometries, they are looking for tools that can keep up with their ever-changing needs,” said Dr. Richard Trihy, Director of Design Methodology, Design Solutions, GLOBALFOUNDRIES.  “By ensuring Cadence’s Physical Verification System support for 65nm to 14nm technology nodes, our mutual customers can now benefit from the in-design physical verification in Virtuoso and Encounter flows.”

Customers can now standardize on PVS for in-design signoff via the seamless integration with Cadence Virtuoso custom IC design platform and Encounter Digital Implementation System, and for full-chip signoff. In-design PVS enables customers to instantaneously detect errors, generate fixing guidelines, incrementally verify the fix, and prevent any new errors while in either the Virtuoso or Encounter platforms. The Virtuoso Integrated Physical Verification System integrates signoff PVS technology into Virtuoso Layout Suite and verifies the design as it is drawn in an interactive “real-time” mode. Timing-aware PVS incremental metal fill in Encounter Digital Implementation System dramatically reduces signoff ECO (engineering change order) turnaround time compared to traditional flows. The certified PVS physical signoff ensures that designs conform to complex rules and matches the desired chip functionality, without compromising on accuracy.

Related news: High cost per wafer, long design cycles may delay 20nm and beyond

“Physical signoff rules and checks continue to grow exponentially due to the growing lithography equipment gap in manufacturing. Through our close collaboration with GLOBALFOUNDRIES and our customers, we continue to deliver the technologies needed to design and sign off complex designs at today’s most advanced geometries,” said Dr. Anirudh Devgan, senior vice president, Digital and Signoff Group at Cadence. “Through the certification of our PVS rule decks for physical signoff, our customers can leverage the best in-design integration with Cadence platforms to enable the fastest time to tapeout.”

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