Scaling to 5nm: A plethora of paths

By Debra Vogler, SEMI

Previous semiconductor technology generations developed more clearly defined “winners” in terms of process technologies and materials choices. As the industry goes below 14nm, however, it appears that there will be multiple technologies used along the way. For lithography, that includes the further extension of 193i, plus the inclusion of EUVL, directed self-assembly (DSA), maskless lithography (ML2), and more. For transistor scaling, it could be some combination of nonplanar device structures and non-silicon materials (e.g., III-V), but it could also mean that, depending on the application, a company might want to choose a nontraditional scaling path such as 3D integration.

Lithography: keeping all options open

Immersion lithography at 193nm is still very much alive — and while the industry works to ready EUVL for high-volume manufacturing (HVM), Nikon’s position has been to maintain the 193 infrastructure and keep improving 193 tools to support multiple patterning and other technologies that are coming into play. “It was premature to declare 193i dead,” according to Stephen Renwick, senior research scientist at Nikon Research Corporation of America. “It’s still very much alive and a viable option as we go into 10nm and 7nm (Figures 1, 2).” As part of its immersion lithography extension pipeline, the company’s model S622D is shipping now and is being used at 14nm, with end users looking to extend it to the 10nm logic node. “The S630D is coming soon and is intended to be used at 10nm and extended to the 7nm logic node,” said Renwick, who will present at the “Readiness of Advanced Lithography Technologies for HVM” session (part of the new Semiconductor Technology Symposium) at SEMICON West 2014 (

Figure 1

Figure 1. Lithography technology trends. Source: Nikon


Screen Shot 2014-04-28 at 7.16.37 PM

Figure 2. Options for different nodes. Source: Nikon

One next-generation lithography (NGL) technology that Nikon has been evaluating is directed self-assembly (DSA). It is the scanners that make the guide patterns used to guide the block copolymers that self-assemble, so the company was interested in anticipating what might be needed in terms of additional performance requirements on 193 immersion scanners (e.g., overlay, CD uniformity) to make the guide patterns. Rathsack, et al., (Adv. Litho. 2012, Proc. SPIE, #8323) have achieved 12.5nm lines/spaces using 100nm guide patterns, which are approximately the 7nm node requirements. According to Renwick, to meet these DSA requirements at 7nm, a 193i scanner needs an overlay ≤2nm and single-digit CDU — requirements the company can fulfill. The company’s S630D is already able to meet the requirements and the S622D is coming along, noted Renwick.

Also working to extend 193i lithography with complementary solutions such as DSA and maskless lithography (ML2) is CEA-Leti, with its IMAGINE (for ML2) and IDEAL (for DSA) programs. The IMAGINE Program is charged with developing and industrializing electron beam high-throughput maskless lithography developed by MAPPER Lithography. Members include: MAPPER, TSMC, STMicroelectronics, Nissan Chemical, TOK, JSR Micro, Sokudo, TEL, Mentor Graphics, and Aselta Nanographics. According to Serge Tedesco, lithography program manager at CEA-Leti, ML2 offers a production price reduction for low- and mid-volume applications. “This technique appears quite attractive for coping with the increasing difficulties relative to the patterning of critical levels, such as contact layers, and the cut level in the case of complementary lithography,” Tedesco told SEMI.

At the present time, the IMAGINE program’s pre-production Matrix 1.1 platform is making steady progress. The installation at Leti began in July 2013 and the first exposure is scheduled for June 2014. The Matrix 1.1 comprises 1300 x 49 beams to reach a throughput target of 1wph. The specifications on this pre-production platform are identical to the production version (i.e., 32nm L/S, 10nm overlay). To build up the infrastructure to support the platform, Leti has interfaced the tool with the Sokudo DUO track. Work is on-going with resist suppliers and the data base infrastructure for e-beam proximity correction (EPC) is being handled by Aselta — a Leti start-up. Additionally, Mentor Graphics and Mapper announced a partnership to support the Matrix data format.

The next phase of the pre-production IMAGINE program is getting the platform to 10wph (Matrix 10.1) using 13000 beams. The Matrix platform roadmap places the 10.1 phase starting at about Q4/14 and going until Q1/15. After that comes development of an HVM tool — the Matrix 10.10 — that will have 10 clustered 10wph/module modules for a throughput of 100wph (Figure 3).

Figure 3. IMAGINE roadmap. Source: CEA-Leti

Figure 3. IMAGINE roadmap. Source: CEA-Leti

Regarding Leti’s DSA activities, Tedesco reports that its IDEAL program is making progress on both the materials and process integration fronts. “Resolution, CD control and defectivity are in the range of what will be needed for implementation of the technology,” said Tedesco. He added that the addition of partners such as TOK, ASML, and Mentor Graphics will ensure the infrastructure will be ready. Tedesco will also present at the “Readiness of Advanced Lithography Technologies for HVM” session.

Also on the DSA front, another European project called PLACYD was launched earlier this year by Arkema, Leti, and 9 other European partners. The project will set up a dedicated materials pilot line at Arkema (in Lacq, France) to supply block copolymers for DSA lithography. The objective is to provide such materials that are precisely defined, with high purity, and that are highly reproducible on an industrial scale.

Regarding ML2 and DSA, Tedesco is rather upbeat about the future. “Complementary and cost-effective solutions, such as DSA and ML2 could help extend 193i much further than originally anticipated,” he said.

Scaling transistors: a matter of function

It may be less clear what will be sorted out for transistor scaling as the industry gets closer to the 5nm node. There are many choices that will need to be made just for materials, i.e., substrate, channel, and gate. Add in the different types of device architectures — FinFET, gate-all-around, and even unconventional choices such as tunnel FETs and nanowires — and you have a toss-up delimited by device application. An Chen, senior member of the technical staff at GLOBALFOUNDRIES and Chair of the ITRS Emerging Research Devices Working Group, told SEMI that there is no consensus on the device/material choices. Will building a consensus even make sense? It seems unlikely. “Companies may run into different challenges and reach different conclusions on the same technology,” said Chen. “The maturity level of technology development among different companies will also affect their opinions on technology options.” Adding to the mix is the fact that different applications require different device characteristics, so a particular company’s focus could affect its preferences on technology options, he observed. Chen will present at the “Getting to 5nm Devices: Evolutionary Scaling to Disruptive Scaling and Beyond” STS session at SEMICON West.

The plethora of directions and choices is not the only wrench in the works. “The increasing cost of R&D and decreasing return in the semiconductor industry do not appear to be sustainable,” stated Chen. Still, he doesn’t think that development will slow down because of funding challenges, though he does believe that fewer and fewer companies will be able to afford the high cost of R&D for scaling. Indeed, even some consortia are collaborating with each other and more companies may start looking for alternatives, he observed. “There is a lot of research on beyond-CMOS technologies, but they seem to be more suitable to augment CMOS rather than to replace CMOS. And low power has been a common feature of many beyond-CMOS devices, which could become increasingly useful because of applications driven more and more by portability and mobility.” Chen further observed that functional diversification or enhancement — e.g., 3D integration — may enable better system functionalities without relying on scaling.

The term “functional diversification” has been used by ITRS participants when they started to look into the “More than Moore” (MtM) directions the industry could take, explained Chen.  “Instead of being driven by scaling (or nodes), MtM focuses more on functionalities that may be enabled by technologies beyond digital computing,” said Chen. Examples of such functionalities are analog, sensing, and energy harvesting.

Regarding funding sources and possible disruptive technologies, Chen noted that a few years ago, the industry was talking about what technology can be found to extend scaling substantially beyond extreme CMOS. Research funded by programs such as DARPA, SRC, etc., might not be the most appropriate uses for such technologies. “Many of them may be better used — together with a CMOS platform — to create new functions or improve efficiency,” said Chen. But such programs might not necessarily help with physical scaling.

Hear from the experts — live!   This year, SEMI announced the new Semiconductor Technology Symposium (STS), to be held July 8-10 as part of the SEMICON West 2014 technical and business program agenda. The new paid program addresses the most important and critical issues facing the future of semiconductor manufacturing in a new and more technical conference format. More information and pricing for the STS sessions available here:

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2 thoughts on “Scaling to 5nm: A plethora of paths

  1. Diogenes Cicero

    What will it take for industry “pundits” to recognize imprint as a viable candidate. You would think anyone who can posit x-ray (a.k.a. EUV) and e-beam direct write as viable candidates for NGL after 30+ years and billions of dollars, might consider imprint possible. X-ray and EBDW have been dismal failures and will never earn a satisfactory return, even IF they go into production…..which is highly doubtful. Between Canon and Toshiba, and a tiny fraction of the investment in x-ray and EBDW, watch imprint for NVM.

  2. Sang Kim

    Sang kim

    For long channel transistors like Intel 22nm FDFinFETs the transistor on-current mainly comes from the fully depleted region. That is why Intel emphasizes FD(fully depleted). For 5nm channel or gate length, Lg the transistor width(TrW) must be ≥ Lg or channel length in order to suppress transistor leakage current or short channel effects. For TrW=5nm, however, there is no longer fully depleted region because the 5nm TrW is too small to have the depleted region. Instead, the entire 5nm TrW is now inverted because the TrW=5nm is so narrow that the inversion current becomes predominant. Therefore, the 5nm node will be the end of scaling, not a plethora of paths.


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