Date: September 2014 (Date and time to be announced)
Free to attend
Length: Approximately one hour
Speakers: To be announced
Registration will be available soon. Click here to pre-register.
Back-end packaging is increasingly important to semiconductor device form factor, thermal and power performance, and costs. Compounded by the demand for lead-free processing and the soaring cost of gold, the industry is developing new approaches to packaging, including redistribution layers (RDL), through silicon vias (TSV), copper pillars, wafer-level packaging (WLP) and copper wire bonding. Experts will discuss these and other approaches in this webcast.
Want to sponsor this webcast? Contact Sabrina Straub.