Date: September 2014 (Date and time to be announced)
Free to attend
Length: Approximately one hour
Speakers: To be announced
Registration will be available soon. Click here to pre-register.
Back-end packaging is increasingly important to semiconductor device form factor, thermal and power performance, and costs. Compounded by the demand for lead-free processing and the soaring cost of gold, the industry is developing new approaches to packaging, including redistribution layers (RDL), through silicon vias (TSV), copper pillars, wafer-level packaging (WLP) and copper wire bonding. Experts will discuss these and other approaches in this webcast.
Sponsored by EV Group and Zeta Instruments
EV Group, Inc. (EVG) is a leading supplier of processing equipment and process solutions for the manufacture of semiconductor components, microelectromechanical systems (MEMS), compound semiconductor, power and nanotechnology devices. Key products include wafer bonding, thin-wafer processing, lithography / nanoimprint lithography (NIL) and metrology equipment as well as photo-resist coaters / developers, and wafer inspection systems. Founded in 1980, EVG services and supports a varied network of global customers and partners all over the world. More information about EVG is available at www.EVGroup.com.
Zeta Instruments is a dynamic start-up company based in Silicon Valley that specializes in wafer defect inspection and metrology instruments. We combine our innovative optics design with advanced software algorithms in products tailored for the target applications in the semiconductor and adjacent markets. In addition to innovative technologies, Zeta Instruments is focused on delivering best-in-class hardware and very user-friendly interfaces. For further details, please contact Zeta Instruments at : www.zeta-inst.com