By Dr. Lianfeng Yang, Vice President of Marketing, ProPlus Design Solutions, Inc.
The ProPlus blog here on Solid State Technology has looked at giga-scale design challenges and, this year, so will the Design Automation Conference (DAC).
On Monday’s program, a pavilion panel sponsored by ProPlus will address “Giga-Scale Design Challenges: Billions and Billions of Transistors.” ProPlus’ Dr. Bruce McGaughy will be a panelist, along with Kelvin Low of Samsung and Mike Gianfagna from eSilicon. Dave Bursky of Chip Design Magazine, Solid State Technology’s sister publication, will act as moderator.
According to the abstract on the DAC website, giga-scale design means super-integration SoCs with 3 billion+ transistors and process technologies starting at 16/14nm FinFETs, approaching 10nm. This produces tera-scale problems for EDA vendors, leading-edge designers and foundries demanding a cooperative solution. The panel of experts will scrutinize emerging challenges of complexity and how to solve them.
As Bruce McGaughy will explain, giga-scale challenges mean extremely large post-layout simulations that call for giga-scale SPICE simulators, such as efficiently simulating giga-scale elements with SPICE-level accuracy. Design for Yield solutions, including accurate and integrated yield analysis and optimization tools, are another example that need to handle large statistical circuit simulations with giga-scale sampling for high sigma circuit design requirements. These giga-scale SPICE simulations were not possible in the past, but have become a necessity today. Modern nano technologies, such as FinFET, further complicate giga-scale design challenges. Foundries, design houses and EDA vendors must work together to tackle such increasing giga-scale challenges in the nano era.
The panel will be held from 11:30 a.m. until 12:15 p.m. on the show floor in the Pavilion (Booth #313).
DAC moves across continents for another pavilion panel sponsored by ProPlus that will be held Monday afternoon from 1:30-2:15 p.m. “China Fabless: Threat or Opportunity?” will be moderated by Junko Yoshida from EE Times. Panelists include Limin He of Cadence, Jin Zhang from Oski Technology and Professor ShaoJun Wei of Tsinghua University in Beijing, China.
The 2013 smartphone market was close to one-billion units, notes the panel description. Chinese brands accounted for 50% of the total. Seventy percent of Chinese phones used apps processors and SoCs designed in China or Taiwan. Panelists will attempt to determine whether the center of gravity of SoC innovation has shifted to China and where funding can be found for fabless chip startups.
With offices in Beijing, Jinan and Shanghai, we have experienced firsthand the tremendous opportunities in China for the semiconductor industry. We’re delighted DAC’s tackling the topic. You will hear insights from panelists with different perspectives. In particular, Dr. Wei, who serves as IC design branch chairman of the China Semiconductor Industry Association (CSIA) in addition to being director of the Institute of Microelectronics at Tsinghua University, will describe real opportunities in the China semiconductor industry. He will offer a look at how China fabless companies are doing.
Both panels were organized by Thomas Wong of Cadence, who serves on the DAC Pavilion Panel Committee, with help from ProPlus.
DAC will be held Monday, June 2, through Wednesday, June 4, from 9 a.m. until 6 p.m. at the Moscone Center in San Francisco. This year’s program includes 16 pavilion panels scheduled Monday, Tuesday and Wednesday. Details on the entire DAC program can be found at www.dac.com.
And, if you’re attending DAC, please stop by the ProPlus booth (#905) to see the latest in DFY and how ProPlus can help you tackle the challenges in giga-scale SPICE simulations and nano-scale SPICE modeling. To reserve a meeting, send email to firstname.lastname@example.org. Additionally, attendees will have a chance to try their luck in our daily raffle drawing session. See you in San Francisco!
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