Synopsys, Inc. today announced the validation of DesignWare IP in the TSMC 16nm FinFET process technology, demonstrating the ongoing collaboration between Synopsys and TSMC to provide designers with proven IP for their advanced system-on-chip (SoC) designs. The silicon success of the DesignWare USB 3.0 femtoPHY IP, Logic Libraries and Embedded Memories in TSMC’s 16nm FinFET process is evidence of both companies’ deep expertise in delivering high-quality IP, enabling designers to integrate needed functionality with less risk and paving the way for the successful deployment of IP in TSMC’s 16FF+ process. Designers developing SoCs in TSMC’s 16nm FinFET process can take advantage of the doubled transistor density, which reduces power consumption by up to 55 percent or increases performance by up to 35 percent compared to TSMC’s 28nm process.
Synopsys’ DesignWare USB, Logic Library and Embedded Memory IP in TSMC’s 16-nm FinFET process, combined with the DesignWare STAR Memory System and DesignWare STAR Hierarchical System embedded test and repair solutions, enable designers to incorporate more functionality into advanced SoCs while meeting high performance, low power and small silicon area requirements. TSMC is using the STAR Memory System to test, repair and diagnose memories in all of its 16FF+ test chips.
The three-dimensional structure of FinFET devices represents a significant change in transistor manufacturing that significantly impacts IP design. Working closely with TSMC and leading customers enabled Synopsys to gain design expertise and a deep understanding of IP architectures. Synopsys’ IP solutions for FinFET implement proven technologies to successfully manage the change from planar to 3-D transistors, including 16nm FinFET and 16FF+. Furthermore, Synopsys provides TCAD and mask synthesis products used by foundries for FinFET process development.
“TSMC’s longstanding collaboration with Synopsys has enabled us to offer designers access to a broad portfolio of high-quality IP solutions for a wide range of TSMC processes,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “Working with Synopsys on the development of the DesignWare Interface, Logic Library and Embedded Memory IP for TSMC’s advanced 16-nm FinFET process extends our long history of success, and puts Synopsys on track to deliver quality IP in the 16FF+ process to reduce integration risk and accelerate time-to-volume production for our mutual customers.”
Synopsys’ DesignWare USB IP has been implemented in more than 3,000 designs and ported to more than 100 process technologies, giving designers immediate access to low-power, small area IP in their required process technology. The DesignWare Logic Libraries and Embedded Memories consist of a broad range of high-speed, high-density and low-power memories and standard cell libraries optimized for maximum performance with the lowest possible power consumption.
Synopsys has optimized the DesignWare STAR Memory System for memory test, repair and diagnostics and DesignWare STAR Hierarchical System for test integration and pattern re-use of all IP on an SoC for TSMC’s 16-nm FinFET process. The hierarchical test and repair solutions enable designers and test engineers to increase test productivity, reduce overall test cost and improve test quality-of-results (QoR).
“Synopsys’ close collaboration with TSMC has enabled us to successfully deliver silicon-proven IP in TSMC’s advanced 16-nm FinFET process and help designers accelerate the adoption of FinFET technology for higher-performance and more power-efficient SoCs,” said John Koeter, vice president of marketing for IP and systems at Synopsys. “The successful DesignWare IP silicon results, combined with the experience gained from developing IP for the 16-nm FinFET process, put us in a strong position to deliver on our 16FF+ roadmap, enabling designers to gain the full benefits of the advanced node and bring differentiated products to market faster.”