Micron Technology, Inc. today outlined their participation in the upcoming 2014 Symposia on VLSI Technology and Circuits scheduled for June 9-13. Along with executive panel appearances, the Micron Research and Development team will feature presentations at the conference on integration of silicon photonics in bulk CMOS and copper resistive random access memory (ReRAM) for storage class memory applications.
The integration of silicon photonics in bulk CMOS presentation details Micron’s research on the development of the first monolithic process flow integrating silicon photonics on operational bulk CMOS. The research demonstrates silicon photonics as a “More-than-Moore’s Law” pathway to enable future high-performance memory applications. This effort is part of a larger project on building a complete photonic processor-memory system that includes research teams from Massachusetts Institute of Technology (MIT), University of Colorado Boulder and University of California, Berkeley. The research was funded by the Defense Advanced Research Projects Agency.
The copper ReRAM cell for storage class memory targets hybrid memory systems that incorporate storage class memory as non-volatile cache or DRAM data backup. This is expected to bolster system efficiency and reduce costs since storage class memory promises higher density than DRAM cache and higher speed than the storage control module. The presentation will introduce ReRAM cell technology meeting the storage class memory performance specifications for a 16gigabit ReRAM with 200megabyte per second write and 1gigabyte per second read speeds. This work focuses on the demonstration of the world’s most advanced ReRAM capability. This technology is being developed in close collaboration with Micron’s research partner Sony Corporation.
Meanwhile, Micron executives will also speak at three VLSI discussions. Scott DeBoer, Vice President of Research and Development, will serve as a panelist June 12 on Emerging Semiconductor Industry Trends and Implications. Ed Doller, Vice President and Chief Memory Systems Architect, will speak June 11 at a Circuits Plenary Session entitled DataCenter 2020: Near-Memory Acceleration for Data-Oriented Applications. Additionally, Mark Bauer, Director of Architecture for the Micron NAND Solutions Group, will serve as a panelist on June 12 discussing Lessons and Challenges for Future Mixed-Signal, RF and Memory Circuits.