Noise cancellation: The new failure and yield analysis superpower

Root cause deconvolution is a quick and cost effective way to determine the underlying root causes represented in a population of failing devices from test data alone.

BY GEIR EIDE, Mentor Graphics, Wilsonville, OR

With 22nm FinFET-powered laptops now available and foundries announcing timelines for single-digit manufacturing nodes, it’s clear not everybody got the memo declaring Moore’s law dead and obsolete. While each new manufacturing node introduces new defect mechanisms, one notable trend is the dramatic increase in number and complexity of design-sensitive defects. This means that in addition to the low yield seen initially as a new manufacturing process is introduced, variability from design to design makes yield a continuing challenge even as the process matures.

The obvious question to ask when you stare at a pile of failing devices is: Why are these devices failing? The pile can represent a number of different defect mechanisms (or root causes). Some may be familiar, while others are new. Some may be easy to find, while others are virtually invisible. Physical failure analysis (PFA) is used to find defects in failing devices, but this is a very costly and time consuming process. Determining what to submit to PFA is therefore a balancing act between controlling expense and finding the relevant defect. Wouldn’t it be great if you could determine the underlying root causes early, and pick the die for PFA that represents the causes of interest in an effective and low cost manner? This is the promise of a new scan test diagnosis technology called root cause deconvolution.

FIGURE 1. Typical application: Root Cause Deconvolution determines root cause distribution and devices most likely to fail for each root cause. Defect courtesy [2].

FIGURE 1. Typical application: Root Cause Deconvolution determines root cause distribution and devices most likely to fail for each root cause. Defect courtesy [2].

Software-based diagnosis of test failures is an established method for localizing defects in digital semiconductor devices. Diagnosis software determines the defect type and location for each failing device based on the design description, scan test patterns, and tester fail data. But diagnosis results contain ambiguity or noise. The diagnosis result for one specific die may point to more than one possible location. Each location may in turn have multiple properties or root causes. For example, the suspect location can span multiple layers (metal3, via4, metal4) while the true root cause is an open defect in just one of these layers. You may observe that many diagnosis results call out net segments that include a particular via type. What you cannot see from the diagnosis results alone is whether that is to be expected or not, i.e. whether this is a common via type or not. This means that plain diagnosis results cannot be used to determine the underlying root cause distribution. Similarly, you may see more bridges in metal3 than metal4, not knowing whether that is to be expected or if it points to a systematic defect. A method called zonal analysis manages this noise by finding relative differences in the diagnosis reports. This method is most effective for identifying hidden systematic defects at fairly high yields, such as the last 1%-2% in high volume manufacturing [1].

But until now there has not been a way to effectively eliminate the noise in the diagnosis results and determine the underlying root causes represented in a population of failing devices. The new root cause deconvolution (RCD) technology is based on Bayesian probability analysis, which is well-known in machine learning applications. It leverages design statistics such as critical area per net segment per metal layer and count of tested cells per cell type. The technology uses a probabilistic model that calculates the proba- bility of observing a set of diagnosis results for a given defect distribution. This model is then used to determine the most likely defect distribution for a given set of diagnosis results.

A typical application of RCD is shown in FIGURE 1. For one wafer, the failing cycles are recorded for devices that failed scan test patterns, and then layout- aware diagnosis is performed (1). RCD analysis is done on the diagnosis results, identifying the under- lying root cause distribution (2). This result can then be compared with equivalent distributions from the same design or comparable designs. Having this data available before any devices are submitted to PFA significantly accelerates the analysis time. You can then select the root cause of interest, in this case the most significant contributor. The RCD analysis will then identify the die that have the largest probability of failing because of this defect mechanism. Before submitting a die to PFA (4), you know where to look for the defect, and also what to look for.

In a comprehensive experiment [3], RCD results for four lots of failing devices correlated to the conclusions reached through inline inspection, failure analysis, and known process changes. RCD is a quick and cost effective way to determine the underlying root causes represented in a population of failing devices from test data alone. This provides significant value to the yield and failure analysis process at fabless semiconductor companies.

References

1. W. Yang, C. Hao, “Diagnosis-Driven Yield Analysis Improves Mature Yield”, Chip Design Magazine, Fall 2011.

2. M. Sharma, et.al., “Efficiently Performing Yield En- hancements by Identifying Dominant Physical Root Cause from Test Fail Data”, IEEE International Test Conference, 2008

3. B. Benware, et.al., “Determining a Failure Root Cause Distribution From a Population of Layout-Aware Scan Diagnosis Results”, IEEE D&T of Computers, Volume 29, Issue 1.

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