2014 iTherm By Dr. Phil Garrou, Contributing Editor iTherm is the Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems. The 2014 iTherm was held concurrently with the ECTC in Orlando, FL. This year’s General Chair was Mehdi Basheghi of Stanford and program chair was Madhusudan of Google. Attendance this year was up 50% to ~ 400. Kumari and co-workers at HP addressed “Air Cooling Limits of 3D Stacked Logic Processor and Memory Dies.” Their goal was to determine how many memory die can be integrated into a package with logic before exceeding the temp limitations of the memory die. Modeling was done for 10nm technology with 24 cores as shown in FIGURE 1. Core power is varied from 1.5 to 3 W (red cores). Stacked memory are 0.5W DRAM. FIGURE 1. Work at HP aimed to determine how many memory die can be integrated into a package with logic before exceeding temperature limitations. Oprins and Beyne discussed the “Thermal Modeling of the Impact of 3D Interposer Materials and Thickness on Thermal Performance and Die-to-die Thermal Coupling.” For the test vehicle shown in FIGURE 2, they observe reducing the thermal conductivity from Si to glass results in an increase in the logic temperature and consequently a lower maximum logic power. The memory temperature at the other hand decreases for decreasing values of the conductivity since the in plane thermal coupling is reduced. This results in an increase of the allowable logic temperature. If the memory heating is included, an increase of the memory temperature can be observed for very low conductivity values. FIGURE 2. imec used this test vehicle to study thermal conductivity. Most applications for interposers combine high power components (logic) and temperature sensitivecomponents (memory). Since the components are thermally coupled in the package, the logic power will be limited by either the temperature limit of the logic or memory, whichever is reached first. This means there is a trade-off between the logic self-heating and the thermal coupling which are impacted differently by the interposer material and thickness choice. It is shown that the Si interposer has a better thermal performance than the glass interposer in case only the logic temperature limit is taken into account and that the Si interposer package thermally outperforms the single chip package, the package-on-package configuration (PoP) and the 3D stacked configuration. In case the memory temper- ature limit and self-heating are taken into account as well, the glass interposer package has a better thermal performance for cases where the memory temperature limit memory is sufficiently lower than logic temperature limit.