Laser spike annealing resolves sub-20nm logic device manufacturing challenges

LSA technology plays an enabling role to overcoming manufacturing challenges for sub-20nm logic devices. 

By YUN WANG, Ph.D., Ultratech, San Jose, CA

Sub-20nm system-on-chip and FinFET devices have specific manufacturing challenges that can be resolved with laser spike annealing (LSA) technology. Over the last decade, new process technologies and materials have emerged, such as strained silicon, high-k/metal gate (HKMG) and advanced silicide. Meanwhile transistor structures have evolved significantly, from bulk planar and PDSOI to 3D FinFET. With dimensions approaching atomic scales, the need for low thermal budget processes offered by millisecond annealing (MSA) becomes more important to precisely control the impurity profiles and engineer interfaces. This article will explain how LSA technology plays an enabling role to overcoming manufacturing challenges for sub-20nm logic devices.

LSA and MSA

The European semiconductor equipment market is expected to grow along with the world market. Global capital spending on semiconductor equipment is projected to grow 21.1 percent in 2014 and 21.0 percent in 2015. According to the August edition of the SEMI World Fab Forecast, semiconductor equipment spending will increase from $29 billion in 2013 to $42 billion in 2015.

In this article the terms LSA and MSA are used interchangeably. MSA can be implemented either by a scanning laser or a bank of flash lamps (FIGURE 1). In both cases, a reduced volume of substrate is heated to high temperature by a powerful light source, which results in fast temperature ramping compared to conventional RTP. Surface cooling in the millisecond time scale is dominated by conductive heat dissipation through the lower temperature substrate, which is several orders of magnitude faster than radiation heat loss or convection cooling through surfaces. The wafer backside is typically heated by a hot chuck or lamps to reduce the front surface peak temperature jump, and in some cases, to reduce the flash lamp power requirement or facilitate laser light absorption. Flash usually requires higher backside heating temperature than the laser option.

FIGURE 1. Simulated temperature distribution in silicon substrate by millisecond nonmelt scanning laser (left) and flash lamp heating (right).

FIGURE 1. Simulated temperature distribution in silicon substrate by millisecond nonmelt scanning laser (left) and flash lamp heating (right).

There are important differences between flash and laser approaches. The flash system provides global heating where the top surface of the entire wafer is heated at the same time. Hence heat dissipation occurs only in one dimension (1D – vertical direction). In addition, the backside needs to be floated to relieve the stress caused by global wafer bending due to the vertical thermal gradient. The laser system, on the other hand, provides localized heating around the scanning beam. The heat dissipation is between two-dimensional (2D) and three-dimensional (3D) (2D for an infinitely long line beam, and 3D for a point source). Since the thermal stress is localized, the backside can be chucked to facilitate heat sinking.

The difference in heat dissipation has a significant impact on the cooling rate, in particular, when long annealing or high intermediate (preheat) temperature is used. FIGURE 2 compares the temperature (T) profiles between laser and flash systems for the same peak surface temperature (Tpk) and dwell time (tdwell— defined as the full-width-half-maximum duration when a fixed point on the wafer sees the laser beam or flash pulse). The latter shows much slower ramp down. This is because once the flash energy is dissipated through the wafer thickness, the cooling is limited by the same radiation loss mechanism as in RTP. For applications relying on non-equilibrium dopant activation, the extra thermal budget due to the slow ramp down could be a concern for deactivation.

FIGURE 2. Comparison of simulated temperature profiles between long dwell laser and flash annealing. Tpk = 1200°C, dwell time = 10ms, preheat T = 800°C for flash. Inset shows details magnified around peak temperature.

FIGURE 2. Comparison of simulated temperature profiles between long dwell laser and flash annealing. Tpk = 1200°C, dwell time = 10ms, preheat T = 800°C for flash. Inset shows details magnified around peak temperature.

LSA technology uses a long wavelength p-polarized CO2 laser with Brewster angle incidence. Previous studies have shown that such configuration has benefits of reduced pattern density effect compared to short wavelength with near normal incidence. A second beam can be added to form a dual beam system that allows more flexibility to adjust the temperature profiles, and expands the process capability to low T and long dwell time.

FIGURE 3 shows different LSA annealing temperature-time (T-t) regimes that can be used to meet various application needs. Standard LSA used in front-end applications has Tpk ranging from 1050~1350°C and tdwell from 0.2~2ms. Short dwell time is beneficial for reducing wafer warpage and litho misalignment, especially for devices with high strain. Long dwell time (2~40ms) adds more thermal budget for defect curing. It can also be used to improve activation and fine tune the junction depth. The low T regime enables applications that require lower substrate and peak annealing temperatures, such as annealing of advanced silicide or new channel/gate stack materials that have poor thermal stability.

FIGURE 3. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

FIGURE 3. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

High-k/metal gate (HKMG)

The impact of MSA on HKMG is thinner equivalent oxide thickness (EOT) due to reduced interfacial layer growth from a lower thermal budget. Lower leakage and better surface morphology are also observed in hafnium-based, high-k films when annealed by a laser.

Incorporating nitrogen into a high-k dielectric film can improve thermal stability, reliability, and EOT scaling. Post nitridation anneal with MSA provides opportunities to stabilize the film with a more precisely controlled nitrogen profile, which is important since excessive nitrogen diffusion can increase interface trap and leakage. Oxygen has a strong impact on the characteristics of HKMG and it is important to control the ambient environment during the gate annealing. Full ambient control capability has been developed for LSA to accommodate this need. FIGURE 4 shows the schematics of our patented micro-chamber approach that allows ambient control to be implemented in a scanning system using non-contact gas bearing. Different process gas can be introduced to accommodate various annealing and material engineering needs.

FIGURE 4. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

FIGURE 4. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

Advanced silicide

Conventional NiSi processing involves two RTA steps. The 1st RTA (200~300°C) forms Ni-rich silicide, and the 2nd RTA (400~500°C) after selective etch of un-reacted Ni forms the desired low resistance NiSi phase. By replacing the 2nd RTA with a high temperature MSA (700~900°C), it can reduce leakage as well as improve performance. The improvement in leakage distribution results from the statistical reduction of Ni pipe defects due to the low thermal budget of MSA.

High temperature promotes phase mixing of Si-rich Ni silicide at the silicide/Si interface and lowers Schottky barrier height (SBH). In conventional RTA, this requires T > 750°C; such high T would lead to morphology degradation, excess diffusion, and higher resistivity. With MSA, because of the short duration, agglomeration does not occur until ~900°C.

To maximize the performance gain, anneal at high T close to the agglomeration threshold is desired. In such a case, minimizing within-die pattern effects and implementing within-wafer and wafer to-wafer temperature control becomes very important.

FinFETs

As FinFETs shrink, interface contact resistance, Rc, becomes more critical (FIGURE 5). A promising path to lower Rc is interface engineering by dopant segregation using pre or post silicide implantation.

FIGURE 5. Parasitic resistance components for different nodes of FinFET, calculated using an analytical model.   of 10-8  -cm2 is used.

FIGURE 5. Parasitic resistance components for different nodes of FinFET, calculated using an analytical model. of 10-8 -cm2 is used.

FIGURE 6. SIMS profiles of Ga-doped (left) p+/n and As-doped (right) n+/p Ge junctions annealed by LSA. For Ga, no diffusion is observed. For As, concentration enhanced diffusion is observed but can be reduced with short dwell time.

FIGURE 6. SIMS profiles of Ga-doped (left) p+/n and As-doped (right) n+/p Ge junctions annealed by LSA. For Ga, no diffusion is observed. For As, concentration enhanced diffusion is observed but can be reduced with short dwell time.

 

Thermal annealing is necessary to repair implant damage and activate dopants in pre silicide implantation scheme, and to drive-in dopants in post silicide case. Using MSA instead of RTA results in more precise dopant profile control, higher dopant concentration at the interface and less potential silicide defectivity, due to the lower thermal budget.

Recently, Ti re-emerged as an option for contact metal because of better thermal stability and potential lower SBH. LSA can be applied to form low Rc Ti/Si contact. In advanced FinFET flow where contacts are formed after source/drain activation and gate stack, low thermal budget process is beneficial to minimize dopant deactivation and unintentional gate work function shift.

In-situ doped selective epitaxial growth is increasingly used to form the raised source/drain for FinFET. There is, however, a limitation in the maximum activation level it can achieve. Activation can be improved using MSA in combination with additional implantation. Drastic FinFET performance improvement has been achieved with co-optimization of conformal doping, selective epitaxial growth, implantation and MSA. In addition to front-end and middle-of-line applications, there are also opportunities at the back-end. One example is low-k curing. For FinFET, low-k is important not only as an inter-Cu dielectric, but also as a transistor-level dielectric to minimize the parasitic capacitance arising from 3D topography. The modulus and hardness of the low-k films can be improved without adversely impacting the k value using MSA.

New channel materials

Below the 10nm technology node, new materials with enhanced transportation, such as SiGe/Ge and III-V compounds, may be needed to meet the performance requirements. These materials have low thermal stability and are lattice mis-matched with the Si substrate, as a result physical integrity during thermal annealing is a very big concern. Low thermal budget processing by MSA provides a way to alleviate this issue. For example, studies on SiGe/Si heterostructures have shown that MSA can enable a higher annealing temperature than RTA, without strain relaxation or structural degradation. This results in improved activation. With MSA, junctions with enhanced activation and reduced diffusion can be obtained.

Summary

We have reviewed various applications of millisecond annealing for advanced device fabrication. As new materials emerge and device dimensions approach the atomic scale, precise thermal budget control becomes critical. This opens new opportunities for short time scale annealing. In addition to the traditional dopant activation and impurity profile control, MSA can also be used for interface engineering and material property modifications (structural, electrical, chemical, and mechanical). In general, if a desired process has higher thermal activation energy than an undesired process, application of high temperature, short duration annealing is beneficial.

YUN WANG, Ph.D., is Senior Vice President and Chief Technologist of Laser Processing Ultratech, San Jose, CA.

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