Process Watch: Fab managers don’t like surprises

By Douglas G. Sutherland and David W. Price

Author’s Note: This is the fourth in a series of 10 installments that explore fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights their implications. Within this article we will use the term inspection to imply either defect inspection or a parametric measurement such as film thickness or critical dimension (CD).

Nobody likes surprises—especially the managers of $10 billion factories. In a dynamic field like advanced semiconductor IC fabrication, there will always be unknowns. However, it is critical to know what you know and know what you don’t know. Every measurement has error. The quality of the decision you make is highly dependent on the uncertainty in the data used to make that decision.

Process control spending is discretionary. Fabs will invest to the point that they believe the return on investment is favorable. It may make financial sense to sample less, skip certain measurements, or use a less capable inspection/metrology tool. However, the fab must always face facts and quantify the level of risk associated with these decisions. The stakes—missing an excursion resulting in costly yield loss—are too high to live in denial.

The fourth fundamental truth of process control for the semiconductor IC industry is: 

Always quantify your lots at risk when making changes to your process control strategy

Quantifying your lots at risk equates to understanding the uncertainty in your measurement. This is a basic concept that most factory engineers learned at some point during their education, however, it is also one of the most tedious of tasks. As a result, this portion of the analysis is skipped more often than we care to admit.

Within process control there are really only two types of risk: Alpha risk and Beta risk. Alpha risk is a false alarm; it is when your inspection tells you that the wafer measured is out of control when really there is nothing wrong with the larger process. Beta risk is the opposite of this; it is when your inspection tells you that the wafer you measured was in control but really there is a serious problem. Figure 1 summarizes the difference.


Figure 1. Definition of Alpha risk and Beta Risk

Alpha and Beta risk arise as a result of the inability to consistently make an inspection that accurately represents the process at that point in time. The best way to reduce both types of risk is to make the process itself less variable. There are few, if any, activities in semiconductor manufacturing that are more value-added than driving variability out of the process. It is much easier to spot real changes in the process when the native lot-to-lot variation is low. However, this cannot always be easily achieved and the Alpha risk (the number of false alarms) can sometimes only be reduced by moving the control limits further from the target (raising the upper control limit and / or lowering the lower control limit). Increasing the spread between the control limits will reduce the Alpha risk but it comes at the expense of increasing the Beta risk—it makes the inspection process less sensitive to real excursions.

Just as changing the native variability in the process usually warrants reassessing where to place the control limits, any time the characteristics of the measurement itself are changed (changing the sensitivity of the recipe, changing the area of the wafer that is inspected, changing the size of the review sample, etc.) the position of the control limits also needs to be re-evaluated.

As an example, consider a defect inspection step where 100 percent of the wafer area is inspected. For a particular defect of interest (DOI) the inspection finds between 40 and 60 DOI on each wafer under normal conditions and the upper control limit (UCL) is placed at 61. If the inspection strategy is changed such that further inspections will only sample 50 percent of the wafer area, the range of normal values will change from between 40 and 60 to between 12 and 42 for 50 percent area (or 24 and 84 when normalized back to the full wafer count). The increase in range is a result of the Binomial Probability Theory that quantifies the effect that sometimes there will be a disproportionate number of DOI in the area that was inspected and sometimes there will be a disproportionate number of DOI in the area that was not inspected.

With the stroke of a pen, the decision to reduce the wafer area to 50 percent has tripled the variability in this particular part of the process from a range of 20 to a range of 60 DOI per wafer. In doing so, they have undone months of hard work by a team of engineers who worked diligently to drive the variability out of the process in the first place. The fab manager must now choose to keep the UCL at 61 and suffer many more false alarms or raise the UCL to 85 where they will have approximately the same number of false alarms but be much less sensitive to real excursions.

The impact of changing the inspected wafer area depends on several factors including the average DOI, the native variation and the size of the excursion that one is trying to detect. Figure 2 shows how the percent error changes as a function of wafer area for three different DOI counts.


Figure 2.  Percent Error versus Wafer Area for three different DOI counts.  At 100 percent area there is no error introduced into the measurement. As the area decreases, the error increases. The error is largest for low DOI counts and is bounded by -100% on the low side and unbounded on the high side.

We have chosen the example of wafer area to illustrate the point because it is such a common practice but the same principles apply to all aspects of process control. The measurement is part of the process― when you degrade the quality of the measurement you degrade the quality of the process.

There are many ways in which process control risk manifests itself in the fab. One simple approach is to get in the habit of asking the questions: “how many lots are at risk if I do this?” and, “what are the error bars on this analysis?”

For example, how many lots are at risk if the fab:

  • Skips an inspection step?
  • Uses a less sensitive inspector or pixel size?
  • Reduces the sampling rate?
  • Use a less precise metrology tool?
  • Measure fewer features per wafer?

Changing process control strategy to reduce costs may seem like a short term solution but it is seldom if ever sustainable for one very simple reason: fab managers don’t like surprises!


1)     You Can’t Fix What You Can’t Find, Solid State Technology, July 2014

2)     Sampling Matters, Semiconductor Manufacturing and Design, September 2014

3)     The Most Expensive Defect, Solid State Technology, December 2014

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with over 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

Process Watch blog series: 

Process Watch: The 10 fundamental truths of process control for the semiconductor IC industry

Process Watch: Exploring the dark side

The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”


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