By Zvi Or-Bach, President and CEO of MonolithIC 3D Inc.
Scaling is now bifurcating – some scaling on with 28/22nm, while other push below 14nm.
In his famous 1965 paper Cramming more components onto integrated circuits, Moore wrote: “The complexity for minimum component costs has increased at a rate of roughly a factor of two per year”. Dimensional scaling below 28nm will only increase the ‘component cost’ as we described in Moore’s Law has stopped at 28nm and is detailed in the following tables published recently by IBS.
While there is still a strong effort behind dimensional scaling to 14, 10 and 7nm – and possibly even beyond, a new scaling effort is emerging to reduce the ‘component costs’ and increase integration yet still utilize the 28 nm process node. The semiconductor industry is now going through a bifurcation phase.
This new emerging trend of scaling by factors other than dimensional scaling was recognized early-on by Gordon Moore and was detailed in his 1975 famous IEDM paper “Progress in digital integrated electronics.”. In that paper Moore updated the time scaling rate to every two years and suggested the following factors are helping to drive scaling forward:
- “Die size” – “larger chip area”
- “Dimension” – “higher density” and “finer geometries”
- “Device and circuit cleverness”
A fourth factor should have been added to the list above – improvement in manufacturing efficiency, which ensued from the increase in wafer sizes from 4” to 5” and all the way to the 12” of today, and many other manufacturing improvements.
In the past, all of these factors were aggregated into dimensional scaling as old fabs got obsolete and improvements were implemented predominantly in the new emerging node. Nowadays, as dimensional scaling has reached its diminishing returns phase, we can see a very diverse adaption of technology improvments.
In his keynote presentation at the 2014 Synopsys user group meeting, Art De Geus, Synopsys CEO, presented multiple slides to illustrate the value of Synopsys’ newer tools to improve older node design effectiveness. The following is one of them:
AMD’s recent presentation at ISSCC 2015 clearly illustrates this point by showing device improvements while still staying at the same 28 nm process node, see slide below. As could be seen, major improvements in power, yield, and performance are possible over time without changing the technology node. AMD’s President & CEO Dr. Lisa Su presentation in 2015 Semicon China, reiterated AMD’s technology progress within the same 28nm technology node:
Even more significant would be the adoption of a breakthrough technology. A good example is the SRAM technology developed by Zeno Semiconductor, which has recently been validated on a 28nm process. This new SRAM technology replaces the 6T SRAM bit cell with 1T SRAM (true SRAM – no refresh is needed) providing significant reduction of ‘component costs’ as is illustrated in the following two slides.
This new industry trend was nicely articulated by Kelvin Low of Samsung covered in “Samsung Describes Road to 14nm, FinFETs a challenge, FD-SOI an alternative.” Quoting: “Samsung spent several years developing its 14nm technology and debating which process node it would invest in after 28nm. Low expects that 28nm will still be a popular process node for years to come because of its price …The cost per transistor has increased in 14nm FinFETs and will continue to do so, Low said, so an alternative technology such as 28nm SOI is necessary”. TSMC too is now spending on new R&D efforts to improve their 28 nm as was presented in TSMC 2015 Technology Symposium, introducing new 28nm processes, 28HPC+ and 28ULP. 28HPC+ is for high performance, a speed gain of about 15% for the same leakage, or a reduction of 30-50% in leakage for the same speed. The 28ULP (for ultra-low power) process is for IoT applications with a lower operating voltage of 0.7V (versus 0.9V for 28HPC+). And also new standard cell libraries were developed for this process with 9 and 7 track libraries (compared to 12T/9T before).
“Device and circuit cleverness” as a factor will never stop; however, it is made of a series of individual improvements that will not be enough to sustain a long-term scaling path for the industry. An alternative long-term path will be “Die size” – “larger chip area,” which is effectively monolithic 3D, and manufacturing efficiency, which will have an important role in monolithic 3D.
And who is better to call it than Mark Bohr of Intel? In a recent blog piece “Intel predicts Moore’s Law to last another 10 years” Bohr is quoted predicting “that Moore’s Law will not come to an abrupt halt, but will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.”
And this is also visible in the marketplace by the industry-wide adoption of 3D NAND devices that Samsung started to mass-produce in 2014, and followed with a second generation 32 layer-stack device this year, and forecasting going to ~ 100 layers, as illustrated in their slide:
In the recent webcast “Monolithic 3D: The Most Effective Path for Future IC Scaling,” Dr. Maud Vinet of CEA Leti presented their “CoolCube” monolithic 3D technology, which was followed by our own, i.e., MonolithIC 3D, presentation. An important breakthrough presented by us was a monolithic 3D process flow that does not require changes in transistor-formation process and could be easily integrated by any fab at any process node.
Finally, I’d like to quote Mark Bohr again as we reported in our blog “Intel Calls for 3D IC”: “heterogeneous integration enabled by 3D IC is an increasingly important part of scaling” as was presented in ISSCC 2015.
This is illustrated nicely by the following figure presented by Qualcomm in their ISPD ‘15 paper titled “3D VLSI: A Scalable Integration Beyond 2D.”
In summary, the general promise of Moore’s Law is not going to end any time soon. Yet it is not going to be the simple brute-force x0.7 dimensional scaling that dominated the industry for the last 5 decades. Quoting Mark Bohr again, it “will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.”
A good conference to learn about these new scaling technologies is the IEEE S3S ‘15, in Sonoma, CA, on October 5th thru 8th, 2015. CEA Leti is scheduled to give an update on their CoolCube program and three leading researchers from Berkeley, Stanford and Taiwan’s NLA Lab will present their work on advanced monolithic 3D integration technologies.