Process Watch: The most expensive defect – Part 2

By David W. Price and Douglas G. Sutherland

Author’s Note: This is the seventh in a series of 10 installments that explore fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights its implications.

The December 2014 edition of Process Watch suggested that the most expensive defect is the one that goes undetected until the end of line. Indeed, undetected excursions typically result in the scrap of millions of dollars per year of defective semiconductor chips.

But many electronics suppliers and OEMs would argue that the consequences of field failures (reliability defects) are much worse than those of non-functioning devices detected at electrical test (killer defects). Reliability defects result in angry customers, expensive failure analysis, the possibility of lost business, or worse. Consider all the IC devices in places such as automobiles, airplanes, and medical diagnostic and treatment equipment. Reliability in these applications is critical—devices simply cannot fail out in the field. Hence, many fabs place a high priority on reducing the potential for reliability defects.

The seventh fundamental truth of process control for the semiconductor IC industry is:

Improving Yield Also Improves Device Reliability.

For a well-designed process and product, early-life factory reliability issues are dominated by random defectivity. This correlation has been confirmed by numerous researchers over the last two decades [1-6]. More recently, the authors interviewed the quality managers at multiple automotive OEMs who confirmed that the vast majority of reliability failures were ultimately traced to random defectivity in the fab.

Latent vs. Killer Defects:

By definition, a killer defect (a.k.a. yield defect) is a defect that causes the device to fail at t = 0 (electrical test). We use the term “latent defect” (a.k.a. reliability defect) to refer to a defect that causes the device to fail at t > 0 (burn-in to ~6 months).

The relationship between yield and reliability stems from the observation that the same defect types that impact yield also impact reliability. The two are distinguished primarily by their size and where they land on the device structure, as shown in Figure 1.

Figure 1. The same defect types that impact yield also affect reliability. They are distinguished primarily by their size and where they land on the die structure.

Figure 1. The same defect types that impact yield also affect reliability. They are distinguished primarily by their size and where they land on the die structure.

Experiments conducted at multiple device manufacturers have shown that for every 100 killer defects that cause yield loss, there are approximately 1-2 latent defects that will result in a reliability failure. This relationship between killer and latent defects is unequivocal and applies to a broad spectrum of defect types. Furthermore, the preponderance of these defects also correlates with overall defectivity. In other words:

  • Lots with poor yield also have poor reliability
  • Wafers with poor yield also have poor reliability
  • Die locations with poor yield also have poor reliability

For this reason, many fabs will ink out a good die if it is in a suspicious neighborhood on the wafer. These good dies, located in neighborhoods where the surrounding dies fail (Figure 2), have a higher probability of a latent defect, which may activate in the field and create a reliability problem.

Figure 2. A good die in a bad neighborhood. Even though the highlighted die may pass final test, there is an elevated likelihood that this die represents a potential reliability problem. Many device manufacturers would ink out such a die at final test.

Figure 2. A good die in a bad neighborhood. Even though the highlighted die may pass final test, there is an elevated likelihood that this die represents a potential reliability problem. Many device manufacturers would ink out such a die at final test.

Reliability Defect Reduction Strategies

IC makers who supply the automotive industry have long adopted the following strategy: The best way to reduce the possibility of latent (reliability) defects is to reduce the fab’s overall random defectivity levels. This is accomplished through the following:

  1. Increased investment in process control in order to achieve higher baseline yields and fewer excursions for the entire fab (both automotive and non-automotive flows; See Figure 3)
  1. Dedicated automotive process flows that utilize only the most stable process equipment
  1. Use of screening inspections on a few layers in which every wafer is scanned for defects. This is typically accomplished using high speed inspection tools, such as KLA-Tencor’s 8-Series  systems
Figure 3. Fabs set their process control budget by attempting to find the minimum total cost (the cost of process control investment plus the cost of lost yield). For some product types, the total cost must also include the cost of reliability failures. These fabs typically spend more on process control strategies compared to those which are only focused on the cost of lost yield.

Figure 3. Fabs set their process control budget by attempting to find the minimum total cost (the cost of process control investment plus the cost of lost yield). For some product types, the total cost must also include the cost of reliability failures. These fabs typically spend more on process control strategies compared to those which are only focused on the cost of lost yield.

Conclusion

Because yield and reliability defects stem from the same source, reducing the source of yield defects will have the side benefit of also reducing reliability defects. Depending on the nature of the product, this could play a significant role in the fab’s determination of the cost-optimal investment in process control. For more information on the correlation of random defectivity and reliability, please contact the authors or refer to the papers listed below.

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Drs. Price and Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

References:

1. Shirley, Glenn and Johnson, Scott. “Defect Models of Yield and Reliability.” Published lecture #13 for Quality and Reliability Engineering ECE 510 course at Portland State University, 2013. http://web.cecs.pdx.edu/~cgshirl/Quality%20and%20Reliability%20Engineering.htm

2. Roesch, Bill. “Reliability Experience.” Published lecture #12 for Quality and Reliability Engineering ECE 510 at Portland State University, 2013. http://web.cecs.pdx.edu/~cgshirl/Quality%20and%20Reliability%20Engineering.htm

3. Kim et al. “On the Relationship of Semiconductor Yield and Reliability.” IEEE Transactions on Semiconductor Manufacturing, Vol. 18, No. 3 (2005).

4. Riordan et al. “Microprocessor Reliability Performance as a Function of Die Location for a .25um, Five Layer Metal CMOS Logic Process.” 37th Annual International Reliability Physics Symposium Proceedings (1999): 1-11. DOI (http://dx.doi.org/10.1109/RELPHY.1999.761584).

5. Barnett et al. “Extending Integrated-Circuit Yield Models to Estimate Early-Life Reliability.” IEEE Transactions on Reliability, Vol. 52, No. 3. (2003).

6. Kuper et al. “Relation between Yield and Reliability of Integrated Circuits: Experimental results and Application to Continuous Early Failure Rate Reduction Programs.” Proceedings of the International Reliability Physics Symposium (1996): 17-21.

Read more from Process Watch:

Increasing process steps and the tyranny of numbers

Time is the enemy of profitability

Know your enemy

The most expensive defect

Fab managers don’t like surprises

The 10 fundamental truths of process control for the semiconductor IC industry

Exploring the dark side,” “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

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