By Zvi Or-Bach, President and CEO, MonolithIC 3D Inc.
SEMICON West 2015 had a strong and rich undercurrent – the roadmap forward is most certainly 3DIC. Yes, the industry can and we will keep pushing dimensions down, but for most designs the path forward would be “More than Moore.” As Globalfoundries’ CEO Jha recently voiced: It’s clear that More-than-Moore is now mainstream rather than niche. Really it is leading-edge pure digital that is the niche. Instead the high-cost leading edge processes are really niche processes optimized for applications in data centers or for high computational loads, albeit niches with volumes of hundreds of millions of units per year.”
CEA Leti’s CEO in her opening presentation for the SEMICON West–Leti day presented the following slide:
Calling the 28nm as the ‘switch node’ from the homogeneous march of the industry with dimensional scaling to the bifurcation we now see, where “More than Moore” approaches such as SOI and 3DIC are taking on an important portion of future progress.
CEA Leti went even further by dedicating its SEMICON West day entirely to 3D technologies, as is seen in their invitation:
GOING VERTICAL WITH LETI: Solutions to new applications using 3D technologies
- Welcome– Leti’s 3D integration for tomorrow’s devices > N Semeria
- CoolCubeTM: 3D sequential integration to maintain Moore’s Law > Faynot
- Photonics: why 3D integration is mandatory > Metras
- Computing: 3D technology for better performance > Cheramy
- Lighting: 3D integration for cost effectiveness > C Robin
- Nanocharacterization for 3D> Bleuet
- Conclusion– Silicon Impulse > N Semeria
Olivier Faynot, Microelectronic Section Manager at LETI, presented the following slide in his CoolCube presentation.
This illustrates that monolithic 3DIC of 4 tiers could provide the equivalent scaling value of the 5nm node at a far less infrastructure or NRE cost. As the slide states: “New scaling path, compared to 2D.” The time is now for monolithic 3D approaches to take hold a grow.
A similar message is projected by a slide presented by An Steegen of IMEC at their pre-SEMICON Technology Forum:
The same assessment was also presented by Intel’s Jeff Groff from his synopsis of Intel’s Q2 call: “In summary, it seems that Intel is executing fairly well on the process technology side of the business considering the ever increasing difficulty of pushing forward with Moore’s Law. We can expect exciting new structures and materials (just maybe not at 10nm) and an increasing importance of 3-D structures in both logic and memory fabrication.” This resonates with our blog Intel Calls for 3D IC, and was recently voiced by Intel process guru Mark Bohr: “Bohr predicted that Moore’s Law will not come to an abrupt halt, but will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.” Bohr’s ISSCC slide from earlier this year reasserts this:
The key two concerns regarding 3DIC stacking using TSV are (a) Cost, noted in the slide above “Poor for Low Cost,” and (b) Vertical connectivity, as voiced by Mark Bohr: “Intel’s Bohr agrees that 3D structures will become more important. He said the kind of through-silicon vias used for today’s chip stacks need to improve in their density by orders of magnitude.”
These limitations are the driver behind the efforts to develop monolithic 3D technology. Monolithic 3D would provide a very cost effective alternative to dimensional scaling with 10,000x higher than TSV vertical connectivity, as illustrated by the following slide of CEA Leti.
A 1,000x improvement in energy efficiency using monolithic 3D was calculated by Stanford Prof. Subhasish Mitra. His sum-up at a SEMICON West keynote panel: “We have an opportunity for a thousand-fold increase in energy efficiency…from collaboration between dense computing and memory elements and dense 3-D integration of them.”
Until recently, all monolithic 3D process flows required a significantly new transistor formation flow. Since the transistor process is where the majority of the R&D budget and talent is being allocated, and carries with it fresh reliability concerns, the industry has been most hesitant with respect to monolithic 3D adoption. Yet in this recent industry gathering there is a sense that industry wide interest is strengthening for 3D technologies. The success of 3D NAND as the first monolithic 3D industry wide adoption could help this new interest build even faster.
A recent technology breakthrough, first presented in IEEE S3S 2014 conference (Precision Bonders – A Game Changer for Monolithic 3D) introduced a game changer in the ease of monolithic 3D adoption. Enhancement of this breakthrough will be presented in this year’s IEEE S3S 2015. This new monolithic 3D flow allows the use of the existing fab transistor process for the fabrication of monolithic 3D devices, offering a most attractive path for the industry future scaling technology.
A good conference to learn more about these new scaling technologies is the IEEE S3S ‘15, in Sonoma, CA, on October 5th thru 8th, 2015. CEA Leti is scheduled to give an update on their CoolCube program, Qualcomm will present some of their work on monolithic 3D – 3DV, and three leading researchers from Berkeley, Stanford and Taiwan’s NLA Lab will present their work on advanced monolithic 3D integration technologies, and many other authors will be talking about their work on monolithic 3DIC and its ecosystem.
More blog posts from Zvi Or-Bach: