3D NAND Flash Process Integration and Architecture from A to Z


Date: April 24, 2018 at 1:00 pm ET

Free to attend

Length: Approximately one hour

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Since 2006, many of new 3D NAND Flash cells have been proposed and commercialized on the market. Already, we have seen 3D NAND cell structure up to 64L/72L with single or multi-stack NAND string architecture. The memory density on Micron/Intel’s 64L 3D NAND 256 Gb/die reached 4.40 Gb/mm2 (256 Gb/die). In this session, we’ll overview 3D NAND Flash roadmap, products, cell design, structure, materials and process integration. The 3D NAND cell architecture from major NAND manufacturers including Samsung TCAT V-NAND, Toshiba/Western Digital BiCS, SK Hynix P-BiCS and Micron/Intel FG CuA will be reviewed and compared. Current and future technology challenges on 3D NAND will be discussed as well.


Dr_ Jeongdong ChoeDr. Jeongdong Choe, Senior Technical Fellow, TechInsights

Jeongdong Choe is a Senior Technical Fellow for TechInsights. He has a Ph.D. in electronic engineering and over 26 years’ experience including 100+ filed/issued patents in semiconductor process integration for DRAM, (V) NAND, SRAM and logic devices. Prior to joining TechInsights in 2011, he worked as a Team Lead in R&D for SK-Hynix and Samsung where he optimized process and device architectures with state-of-the-art technologies for mass production. Jeongdong has been a member of the ‘Future Technology Roadmap’ and ‘Patent Examination’ committees at Samsung, and has led a Process Consulting Group for advanced/emerging NVM devices such as STT-MRAM, ReRAM, and PCRAM and SOI/FinFET/HKMG device for 2x/1x nm future logic and memory devices. He has also written many articles including DRAM Makers Turn to New Process for Sub 2x/1x nm Cells, and Comparing Leading-Edge 2x/1x nm NAND Flash Memories. Jeongdong annually produces a widely distributed roadmaps for Memory Technology.  At Samsung, as Team Lead of NAND FLASH Process Architecture, he advanced next-generation devices, including 42 nm, 35 nm, 27 nm, 21 nm and 19 nm process nodes with optimized DPT (double patterning technology) for 3x and 2x devices and TPT (triple patterning technology) for 1x devices, as well as for sub-20 nm terabit generation for 3D-NAND, including TCAT and VG-NAND architecture.

Sponsored by Tech Insights:

For over 25 years TechInsights has been a trusted patent and technology partner to the world’s largest and most successful companies including 37 of the top 50 U.S. patent holders. By revealing the innovation others can’t inside the broadest range of advanced technology products, we prove patent value and enable business leaders to make the best, fact-based IP and technology investment decisions.


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