Date: Date and time TBD
Free to attend
Length: Approximately one hour
Registration coming soon.
The slowing down of Moore’s Law even at leading CMOS Fabs due to approaching Physics limits, while at the same time the explosion in demand for chips and systems across a wide range of market segments (compact wearable / portable consumer systems, the transfer and processing of data to and from the cloud, at the high performance end specialized architectures e,g for AI) has revived interest in Dense Off Chip Integration (DOCI ), first used in MCMs (Multi Chip Modules) for mainframes some 3 decades ago.
DOCI can be a lower cost alternative to integration of many functions on a single large chip that is often associated with low fab yields at immature nodes. In the consumer end DOCI is an enabler of compactness and power efficiency. To be accepted in the high performance end DOCI must deliver electrical performance not too inferior to single chips or provide efficient package level integration of heterogeneous designs and Fab technologies e,g. Processor and Memory, that are not easily manufactured on a single wafer. In all cases dense and compact package level interconnects with low parasitics using current and emerging Advanced Packaging (AP) technologies are key to wide adoption of DOCI.
Using metrics like electrical performance, density and cost of package level interconnects we will assess various AP technologies ranging from package substrates/interposers, packages like FO WLPS, flip chip, 2.5d modules, 3d stacks such as PoP, and those using TSVs. Recent commercial examples of integrating processor to memory by different approaches to DOCI will be compared.
Lastly emerging AP technologies (substrates cheaper than dual damascene interposers and TSVs) to reduce the cost of DOCI will be compared and opportunities for further development and implementation identified.
While at Motorola and Intel, Dr. Dev Gupta invented many of the Advanced Packaging technologies ( electroplated solder bump flip chip, robotic assembly, organic substrates w/ and w/o core, pillar flip chip, integrated passives, .. ) that have become industry standards today. The micro pillar and thermocompression flip chip technology he invented at Motorola nearly 25 years ago for Gallium Arsenide PAs is now used for building 3d Memory Stacks. He pioneered and managed the transfer of these AP technologies to high volume manufacturing in both the US and Japan. At APSTL he is responsible for identifying technology gaps, developing new technologies to address them, licensing, turn key engineering of Fabs for Advanced Packaging. He also takes an active role in mentoring and training Customer Engineers. Dr. Gupta has many Patents and Publications and often teaches at Conferences the theoretical aspects of Package Level Interconnects, Advanced Packaging and Systems Optimization. The current emphases at APSTL is to lower the cost Adv. Packaging by replacing TSVs, process innovations in die stacking etc. and license them.
Contact Jenna Johnson about sponsorship opportunities for this event.