Transistor-level challenges get squeaky wheel results

By Dr. Lianfeng YangLianfeng Yang, Vice President of Marketing, ProPlus Design Solutions, Inc.

The squeaky wheel gets the grease, or so it seems in the semiconductor industry, as the high level of the design process seems to get the most attention. Meanwhile, the transistor level appears to have been largely forgotten.

With increasing complexities and scale of electronic system, design and verification have moved up the abstraction level from register transfer level (RTL) to the electronic system level (ESL) with help from high-level synthesis software and other new EDA technologies. Portable stimulus is available at ESL to test specifications and virtual platforms enable early software consideration, for example.

Throughout, transistor-level challenges are ongoing but appear to be largely forgotten. New process technologies, such as FinFET, increasingly stress transistor-level verification tools, in particular, SPICE and FastSPICE simulators, and designer needs are greater. Highly accurate and reliable verification and sign-off tools for large post-layout simulation is one of many.

When designers move to 16/14 nanometer and beyond with FinFETs, accuracy is a priority and essential for characterization, verification and signoff, due to reduced Vdd and the impact of process variations. Device characteristics and physical behavior is more complicated with these process nodes. Circuit size is increasing and design margins are shrinking. Every aspect that contributes to leakage and power must be measured and accurately modeled. The entire circuit, including all parasitic components, has to be simulated accurately.

While circuit designers may not be squeaky wheels, they do need to be confident of their designs, as they’re under the pressure from ever-increasing design and manufacturing complexities and cost. FastSPICE simulators used in final verification and signoff do not offer enough accuracy. This is true for small currents critical to low-power design and achieving sufficient noise margins. Often, FastSPICE simulations rely on special, fine-tuned options and start with non-converged DC, further challenging accuracy.

Designers use FastSPICE to verify timing and power before tapeout. Unfortunately, they can’t be sure of the results, risk expensive respins and missing market windows, for applications sensitive to small current or noise elements, such as advanced memory designs. This is an all-too-familiar scenario where wheels should be squeaking.

What sends the situation out of control is FastSPICE’s lack of a golden to refer. FastSPICE provides many options for designer to tune to trade-off accuracy and speed, which worked in past generations. Such an option tuning strategy, however, becomes unreliable for advanced designs where designers have much less design margin than before. Designers now see more and more failure or inaccurate cases due to fundamental accuracy limitations of FastSPICE.

Traditional SPICE simulators were the “golden” simulator to validate FastSPICE, but only for small blocks as no commercially available SPICE simulator can offer simulation capacity for verification and signoff that FastSPICE used. And such validation can’t automatically scale up. The circuit size continues to increase and giga-scale designs are common. At 16nm and beyond, 3D device structures add greater capacity and accuracy challenges. FastSPICE simply doesn’t offer enough confidence and may introduce unpredictably inaccurate or wrong verification results, which designers don’t want to risk for tapeout.

Well, circuit designers may not be squeaking, but help is on the way nevertheless. A new type of SPICE simulator known as giga-scale SPICE simulators or GigaSpice, is able to support giga-scale circuit simulation and verification with a pure SPICE engine. It features SPICE accuracy and FastSPICE-like capacity and performance through advanced parallelization technology. It does not require option tuning and always converges on DC, making it easy for designers to adopt and offering accurate and reliable results for designers. GigaSpice can be a golden reference for FastSPICE and a replacement for memory characterization, large block simulation and full-chip verification.

The squeaky wheel may be noisy, but a few clever developers have been paying attention to the new developments for transistor-level verification and signoff and are responding.Giga-scale SPICE simulators are fast becoming part of circuit-level design flows for squeaky wheel results.

Dr. Lianfeng Yang currently serves as the ProPlus Design Solutions’ vice president of marketing and general manager of Beijing R&D Center. Previously, he was a senior product engineer leading the efforts on product engineering and technical support for the modeling product line to Asian customers at Cadence Design Systems, Inc. Dr. Yang holds a Ph.D. degree in Electrical Engineering from the University of Glasgow, UK.

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One thought on “Transistor-level challenges get squeaky wheel results

  1. Michael Clayton

    Thanks.
    I remember the joint presentation by ProPlus and IBM a few years ago, great graphics and ideas. McGaughy and Joshi 2012? Those slides blew me away.
    GigaSpice sounds interesting.
    Do you plan a revisit of that IBM-ProPlus new product launch simulation with 3 and 6 sigma DFM efforts using GigaSpice?
    Or show how GigaSpice would improve those 2012 results?
    That older effort used NanoSpice. How does that compare with GigaSpice?
    I am not familiar with many EDA tools, but have made new products based on DFM simulation methods long ago at Motorola, retired now, just curious about latest ProPlus efforts.

    Reply

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