STMicroelectronics incorporates CWS’ SiPEX in the RF PDK H9 SOI FEM

Coupling Wave Solutions, S.A. (CWS) and STMicroelectronics (NYSE:STM) today announced that they partnered together to reduce time-to-market for high-performance radio frequency (RF) silicon-on-insulator (SOI) designs. RF Designers and design managers will now be able to enhance their designs of RF SOI switches that propel the next generation cellular and Wi-Fi communication chips. STMicroelectronics’ product development kits with SiPEX are available immediately.

“We are thrilled to partner with STMicroelectronics to provide our customers with a breakthrough design productivity solution,” said Brieuc Turluche, chairman of the board of directors and chief executive officer of CWS. “SiPEX™ accurately models interactions between devices, back-end-of-line, and silicon on insulator (SOI) substrates enabling RF Front End Module designers to fully simulate layout and design changes in less than 15 minutes, an accomplishment not possible until now. Our tool also helps simulation take into account physical effects that were only measurable on silicon in the past. This enhanced capability is fundamental to successfully designing high-performance RF SOI switches for the next generation communication chips.”

For the first time ever, with STMicroelectronics’ product development kits, customers can simulate the impact of layout geometry on RF switch losses and non-linearities (H2/H3 distortions), including active devices, metal interconnects, and substrate contributions. This design capability is empowered by the interaction of Spice models, Mentor XRC tool, and the SiPEX substrate simulation tool. This is significant because customers will now be able to design RF SOI Switches reaching a level of performance never achieved before.

“RF front-end components are complex to design. The right design tool is critical for our RF SOI customers to close the gap between simulation and silicon measurements, and optimize the layout to achieve the best linearity in their chips. Partnering with CWS allows our customers to eliminate design re-spins and accelerate time-to-market,” said Cyril Colin-Madan, head of Design Platform at STMicroelectronics.

Thanks to the SiPEX tool, substrate-aware RF switch simulation flow is now part of the H9 SOI FEM PDK design kit which supports RF SOI designs integrated in H9 SOI FEM technology for Cellular and Wi-Fi applications.

“By combining H9 SOI STM technology with substrate modeling via the CWS tool, we produce the world’s highest performance SOI Switches for IoT and Smart Phone applications,” said Greg Caltabiano, CEO of ACCO Semiconductor.

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