Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced new optimization capabilities within its holistic, integrated design flow for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology. The integrated flow provides design and analysis capabilities and modeling of cross-die interactions for mobile and IoT applications.
The Cadence tools in the enhanced flow include the OrbitIO interconnect designer, System-in-Package (SiP) Layout, Quantus QRC Extraction Solution, Sigrity XtractIM technology, Tempus Timing Signoff Solution, Physical Verification System (PVS), Voltus-Sigrity Package Analysis, Sigrity PowerDC technology and Sigrity PowerSI 3D-EM Extraction Option. With the new flow, system-on-chip (SoC) designers can:
- Quickly generate netlists among the multiple dies and InFO package in the context of the full system within a single-canvas multi-fabric environment: The OrbitIO interconnect designer efficiently handles multi-die integrations with TSMC InFO technologies to generate top-level netlists that can be directly used for subsequent design steps such as detailed electrical and timing analysis.
- Generate Standard Parasitic Exchange Format (SPEF) directly from the package design database, which greatly eases timing signoff: Rather than using a traditional methodology that requires converting the package design database of an InFO design to an IC design database to generate SPEF, Sigrity XtractIM technology automatically generates SPEF for heterogeneous InFO systems, which accelerates the timing signoff process and speeds time to market.
“We’ve continued to see strong demand from mobile and IoT customers who want to deploy systems based on TSMC’s InFO technology,” said Steve Durrill, senior product engineering group director at Cadence. “By working closely with TSMC, we are enabling our mutual customers to shorten design and verification cycle times so they can deliver reliable, innovative SoCs to market faster.”
“The Cadence flow developed specifically for our InFO technology is an enabler for customers who need to increase bandwidth within small form factors,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “The integrated full-flow includes a comprehensive set of Cadence digital, signoff and custom IC technologies that address this market need, and our collaboration is helping customers to efficiently achieve their design goals.”