Synopsys and TSMC collaborate to develop interface, analog and foundation IP for 12nm finFET process

Synopsys, Inc. (Nasdaq:  SNPS) today announced its collaboration with TSMC to develop DesignWare Interface, Analog and Foundation IP for TSMC’s 12FFC process. By offering a wide range of IP on TSMC’s latest low-power process, Synopsys is enabling designers to take advantage of the low leakage and small area advantages of the new process. Synopsys and TSMC have partnered on the development of Synopsys IP for advanced process technologies for more than two decades, resulting in a robust portfolio of IP supporting process technologies down to 7nm. Synopsys DesignWare IP for the 12FFC process enables designers to accelerate development of mobile SoCs that incorporate logic librariesembedded memoriesembedded test and repairUSB 3.1/3.0/2.0USB-C 3.1/DisplayPort 1.3DDR4/3LPDDR4XPCI Express 4.0/3.1/2.1SATA 6GHDMI 2.0MIPI M-PHY and D-PHY and data converter IP.

“TSMC and Synopsys share a long history of providing designers with a wide range of high-quality IP on TSMC’s advanced FinFET processes,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “By developing IP on the latest TSMC 12FFC process, Synopsys is paving the way for designers to improve their SoCs’ leakage and lower overall costs.”

“As SoCs continue to incorporate more advanced functionality, designers are constantly challenged with meeting aggressive performance, power and area requirements,” said John Koeter, vice president of marketing for IP at Synopsys. “Our close collaboration with TSMC on the development of a broad range of IP for the 12FFC process will ensure that designers have timely access to the high-quality, proven IP solutions they need to achieve their design goals and quickly get their product to market.”

Synopsys is a provider of high-quality, silicon-proven IP solutions for SoC designs.

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