Synopsys, Inc. (Nasdaq: SNPS) today announced that TSMC has certified the complete suite of products in the Synopsys Galaxy Design Platform for the most current version of 12-nanometer (nm) FinFET process technology. This 12nm certification brings with it the broad body of design collateral, including routing rules, physical verification runsets, signoff-accurate extraction technology files, SPICE correlated timing and interoperable process design kits (iPDKs) for this latest FinFET process. Synopsys Custom Compiler design solution support is enabled through an iPDK.
To accelerate access to this power-efficient, high-density process, IC Compiler II place-and-route system has been enabled to support new standard cell architectures seamlessly co-existing with 16FFC intellectual property (IP). Recent collaborations have resulted in enhancements to IC Compiler II’s core placement and legalization engines ensuring maximum utilization while minimizing placement fragmentation and cell displacement. The 12nm ready iPDK enables designers to use Custom Compiler’s layout assistant features to shorten time in creating FinFET layouts.
“This power-efficient, high-density node offers a broad set of opportunities to our customers, enabling them to deliver highly differentiated products,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Our ongoing collaboration with Synopsys is helping expedite designer access to 12-nm process technology.”
“The long-standing collaboration between Synopsys and TSMC continues to be key in bringing accelerated access to new process technology nodes,” said Bijan Kiani, vice president of product marketing for the Design Group at Synopsys. “With the Galaxy Design Platform certified for 12nm readiness, our mutual customers are enabled to speed up development and deployment to accelerate their time-to-market.”