Synopsys IC Validator physical signoff verifies 10 billion+ transistors within hours

Synopsys, Inc. (Nasdaq:  SNPS) today announced that its IC Validator was successfully deployed on some of the industry’s largest and most advanced designs to accelerate design rule checking (DRC) closure. Through near-linear distributed processing and efficient resource management, IC Validator delivers industry-leading turnaround time, enabling physical signoff within hours on designs with 10 billion+ transistors. Technology advancements in the latest releases of IC Validator reduce both memory and disk usage requirements by 2x. This significant improvement in resource efficiency enables excellent performance scaling to several hundreds of CPUs by taking advantage of the smaller and more readily available machines in the customers’ existing compute farms.

“Increasing manufacturing complexity at advanced nodes makes it challenging for customers to complete physical signoff within schedule,” said Bijan Kiani, vice president, product marketing, Design Group at Synopsys. “Through high-performance scalability and readily available, optimized runsets from all major foundries, IC Validator is providing our customers with the fastest path to production silicon.”

IC Validator, part of the Synopsys Digital Design Platform, is a comprehensive and highly scalable physical signoff solution including DRC, LVS, programmable electrical rule checks (ERC), dummy fill and DFM enhancement. IC Validator is configured for today’s extremely large designs by enabling 8 CPUs with a single license. It uses both multi-threading and distributed processing over multiple machines to provide near linear scalability benefits that extend to several hundreds of CPUs. IC Validator enables coding at higher levels of abstraction and is architected for scalability to maximize utilization of mainstream hardware, using smart memory-aware load scheduling and balancing technologies.

IC Validator is a companion product to Synopsys IC Compiler™ II In-Design physical signoff. In-Design allows place-and-route engineers to perform independent signoff-quality analysis earlier, before the design is finalized and while correction can be automated. In-Design technology enables new high-productivity functionality within the place-and-route environment, including automatic DRC repair, improved timing quality-of-result with timing-aware metal fill, and rapid ECO validation. In-Design physical signoff eliminates expensive iterations with downstream analysis tools and maintains a convergent design flow to physical signoff.

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