SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that UltraSoC will provide debug and trace technology for the SiFive Freedom platform, based on the RISC-V open source processor specification as part of the DesignShare initiative. UltraSoC’s embedded analytics IP will be available through the recently announced SiFive DesignShare ecosystem that gives any company, inventor or maker the ability to harness the power of custom silicon. UltraSoC’s debug and trace functionality will enable users of the Freedom platform to access a wide variety of tools and interfaces to use in their developments.
The DesignShare concept enables an entirely new range of applications. Companies like SiFive, UltraSoC and other ecosystem partners have developed efficient, pre-integrated solutions to lower the upfront engineering costs required to bring a custom chip design based on the SiFive Freedom platform to realization. The partnership between SiFive, originator of the industry’s first open-source chip platform, and UltraSoC, the industry leader in vendor-neutral on-chip debug and analytics tools, significantly strengthens the ecosystem surrounding RISC-V, the open source processor specification which is often dubbed “the Linux of the semiconductor industry.”
“SiFive was founded with the mission to disrupt the semiconductor industry by leveling the playing field for anyone who wants to develop custom silicon,” said Naveed Sherwani, CEO of SiFive. “The DesignShare ecosystem enables aspiring system designers with the tools they need when designing their SoC. We’re thrilled to welcome UltraSoC to the DesignShare ecosystem and look forward to seeing the innovations our collaboration brings to the market.”
UltraSoC’s IP simplifies the development of systems on chip (SoCs) and provides embedded analytics features that enable chip makers to cut development costs significantly and increase the profitability of their projects. The company has taken a leading role in producing a specification for RISC-V processor trace functionality, which UltraSoC and SiFive intend to work together with the RISC-V Foundation to incorporate fully into the RISC-V standard. Trace is a fundamental requirement for developers working with any processor architecture, allowing engineers to view the behavior of their programs in detail, isolating bugs and identifying areas for improvement. UltraSoC and SiFive IP fully supports this recently released trace specification.
“UltraSoC is committed to increasing the number of silicon design starts, and our participation in DesignShare with SiFive is a natural extension of that work,” said Rupert Baines, CEO of UltraSoC. “We are committed to driving the acceleration of the democratization of the semiconductor industry, both through our membership in the RISC-V Foundation and via individual partnerships like this one with SiFive. Making UltraSoC’s IP available through the DesignShare model will enable chipmakers everywhere to leverage the benefits of open source hardware and introduces new innovative designs to the market.”
Rick O’Connor, executive director of the RISC-V Foundation, commented: “The idea behind the open source movement is that one doesn’t have to design everything from scratch. The idea behind DesignShare is to help speed the development of new silicon designs by reducing the barriers of cost, process and integration that have traditionally held back innovation in the semiconductor industry. SiFive, UltraSoC and the other companies that are making their IP available through DesignShare are fundamentally enabling this revolution in an otherwise stagnant industry.”
SiFive was founded by the inventors of RISC-V – Andrew Waterman, Yunsup Lee and Krste Asanovic – with a mission to democratize access to custom silicon. In its first six months of availability, more than 1,000 HiFive1 software development boards have been purchased and delivered to developers in over 40 countries. Additionally, the company has engaged with multiple customers across its IP and SoC products, started shipping the industry’s first RISC-V SoC in November 2016 and announced the availability of its Coreplex RISC-V based IP earlier this month. SiFive’s innovative “study, evaluate, buy” licensing model dramatically simplifies the IP licensing process, and removes traditional road blocks that have limited access to customized, leading edge silicon.
UltraSoC allows designers to create an on-chip infrastructure that non-intrusively monitors a chip’s behavior – both hardware and software. In development, engineers can use this IP to gain an intimate understanding of the interactions between on-chip processor blocks, custom logic, and system software. The company joined the RISC-V Foundation in 2016, with a mission to provide the RISC-V community with secure, independent on-chip development and debug capabilities; earlier in 2017 it offered its RISC-V processor trace specification for adoption by the RISC-V Foundation as part of the open source specification.