Date: October 3, 2017 at 1 p.m. ET
Free to attend
Length: Approximately one hour
Conventional planar flash memory technology is approaching critical scaling limitations that are driving the transition to 3D solutions. 3D NAND is expected to scale in height, from 16-bit-tall strings to string heights of more than 128 bits. Meanwhile NAND makers will find ways of placing these strings closer to each other through more aggressive lithography.
Join the analysts from TechInsights as they explore 3D NAND flash technology from a process, circuit and systems perspective.
With the boom in 3D NAND technology over the last couple of years, all the major NAND manufacturers such as Samsung, Toshiba, Western Digital (SanDisk), Micron, Intel and SK Hynix have already released their cutting-edge 3D NAND commercial products with 64L. Compared to their previous 32L (or 36L) and 48L, memory density per unit cell array area reached up to 3.4 Gb/mm2 which is 2.7 times higher than 15 nm 2D NAND TLC. This year, the new QLC products were introduced, which further scaled development down to n+1 (96L) and n+2 (128L). Every NAND manufacturer keeps their own 3D NAND architecture, and we’ll explore them in more detail and discuss future 3D NAND technology trends and expectations.
With the exception of the memory cell array layout, most 3D NAND flash manufacturers have similar on die peripheral circuit block arrangements, as seen in their previous planar NAND flash products, with the exception of Micron’s latest 32L flash product. In this portion of the presentation, we will look at 3D NAND die photographs and compare die cross sections to identify some of the major differences in circuit implementation and layout arrangements. Challenges in 3D NAND circuit extractions including metal line access for internal signal probing (waveform analysis), memory addressing and programming algorithms will also be discussed.
There are many similarities between implementations of SSDs, but it is their differences with the use of latest NAND flash devices (especially 3D NAND), that have become of great interest for systems analysis, and will be the topic for discussion in this segment. One of the latest systems analyzed by TechInsights showed many interesting new features and differences in operation, on even simple de-facto standard methods of operation, such as addressing a NAND flash device, as well as read-retry situations.
Mohammad Ahmad, Architect
Mohammad Ahmad is an Engineering Solutions Architect in the IP Services group at TechInsights. He has extensive experience with the latest non-volatile semiconductor memory devices, and provides technical support and patent analysis to help global clients maximize the return on their intellectual property investments. Mohammad is responsible for leading, executing and managing large patent portfolio assessments to identify patents for assertion and divestiture and for determining and executing the required reverse engineering in support of the patent portfolios.
He specializes in reverse engineering including circuit extraction, functional testing and internal waveform probing of various semiconductor memories (NAND and NOR Flash, embedded and system memories, DRAM and SRAM). Patent claims analysis, evidence-of-use detection, claim chart documentation, prior art searches and patent/portfolio evaluation and mining.
Dr. Jeongdong Choe, Senior Technical Fellow
Jeongdong Choe is a Senior Technical Fellow for TechInsights. He has a Ph.D. in electronic engineering and over 26 years’ experience including 100+ filed/issued patents in semiconductor process integration for DRAM, (V) NAND, SRAM and logic devices. Prior to joining TechInsights in 2011, he worked as a Team Lead in R&D for SK-Hynix and Samsung where he optimized process and device architectures with state-of-the-art technologies for mass production.
Jeongdong has been a member of the ‘Future Technology Roadmap’ and ‘Patent Examination’ committees at Samsung, and has led a Process Consulting Group for advanced/emerging NVM devices such as STT-MRAM, ReRAM, and PCRAM and SOI/FinFET/HKMG device for 2x/1x nm future logic and memory devices. He has also written many articles including DRAM Makers Turn to New Process for Sub 2x/1x nm Cells, and Comparing Leading-Edge 2x/1x nm NAND Flash Memories. Jeongdong annually produces a widely distributed roadmaps for Memory Technology.
At Samsung, as Team Lead of NAND FLASH Process Architecture, he advanced next-generation devices, including 42 nm, 35 nm, 27 nm, 21 nm and 19 nm process nodes with optimized DPT (double patterning technology) for 3x and 2x devices and TPT (triple patterning technology) for 1x devices, as well as for sub-20 nm terabit generation for 3D-NAND, including TCAT and VG-NAND architecture.
Tarek Alhajj is an Engineering Solutions Architect in the Intellectual Property and Technical Services group at TechInsights where he creates solutions for complex technical and intellectual property problems, especially those involving memory systems.
In his previous role with the company, Tarek was an Engineering Analyst in the systems and software analysis group, where he performed in depth analysis of various circuits and systems, mostly within downstream products, through a combination of circuit extraction, electrical functional testing and literature research. He has analyzed and tested numerous commercial electronic devices for the purposes of intellectual property support, technical intelligence and research and development. His contributions to the development of reverse engineering and testing techniques, particularly for memories and memory systems such as NAND flash and SSDs, greatly enabled detailed analysis of complex systems. Tarek then moved on to Team Lead in the systems and software analysis group to lead and manage a team of engineers.
Prior to TechInsights, he worked for MOSAID Technologies as a Patent Licensing Engineer where he lead the portfolio management, including the due diligence, licensing and litigation of all flash memory and flash memory systems patent portfolios.
Tarek received a B.Eng. degree in Electrical Engineering from Carleton University, Ottawa, Canada, and an M.A.Sc. degree in Electrical Engineering from McGill University, Montreal, Canada. His studies and research focused mainly on characterization and system level behavioral modeling of complex mixed-signal circuits and systems.
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