Surface preparation technology provides pristine and stable hydrogen passivated semiconductor surfaces

A new technology enables dramatically lower thermal budget capability that is enabling to thermal processes like epitaxy, CVD and diffusion, without any semiconductor material consumption.

BY ROBERT PAGLIARO, RP Innovative Engineering Solutions, LLC, Mesa, AZ

As semiconductor based electronic devices have become smaller, faster, smarter, 3-dimensional, and multi-functional the methods and materials required to fabricate them demand novel approaches to be developed and implemented in the device manufacturing facilities. Amongst the most challenging requirements are the need to lower the thermal budgets of the front end thermal processes and to minimize the semiconductor material consumption that comes with the conventional oxidizing (hydrogen peroxide and ozone based chemistries) wet cleaning processes chemistries such as APM, HPM, SPM and SOM.

A novel wet surface preparation method that removes existing surface contamination and native oxide from semiconductor surfaces and then passivates them with a pristine and stable hydrogen passivated surface has been developed and commercialized by APET Co, Ltd. in a system called the TeraDox. This patented technology enables dramatically lower thermal budget capability that is enabling to thermal processes like epitaxy, CVD and diffusion, without any semiconductor material consumption.

The TeraDox system is an enhanced version of the APET FRD (HF etching, Rinse and Dry). The name TeraDox implies the ability to provide a process chemistry with < 1 ppb impurities, particularly dissolved oxygen, which allows for producing pristine and stable H-passivated semiconductor surfaces. Dilute HF and HCl (dHF and dHCl) are the etching chemistries used for removing the native and chemical oxides from Si, SiGe and Ge surfaces. The TeraDox system has a single vessel wet processor and a wafer transfer/drying hood that allows for a segue between the load, chemical fill, etch, insitu-rinse, dry and unload steps of the process sequence, while keeping the process chemistry and the wafers in a continuous ambient of ultra- pure N2. This equipment and process design eliminate the exposure of the wafers to air and minimizes gas perme- ation throughout the entire oxide removal and H-passiv- ation process sequence. These are all critical elements to achieving the best surface quality results. While there are a variety of important parameters towards achieving a pristine and stable H-passivated surface one of the most enabling ingredients to the APET TeraDox process and equipment IP is the PPT level degassing capability for the UPW and aqueous chemicals used in the H-passivation process. The unique UPW and chemical degassing apparatus require an optimized hardware configuration with membrane contactors and facilities used for the vacuum + UHP N2 sweep gas to achieve a DO degassing efficiency > 99.999%. This ultra-high degassing efficiency allows for a Dissolved Oxygen (DO) concen- tration capability of < 100 ppt.

It has been well proven and documented by multiple world-renowned surface scientists [1,2,3] since the late 1980s that the level of dissolved oxygen (DO), as well as other dissolved impurities (such as CO2, TOC, silica and N2), has a direct impact on the efficiency of H-passivation and the native oxide (initial and changing thickness vs. queue time) that follows the removal of native and chemical oxides from semicon- ductor surfaces. Queue time (Q-time) is the amount of time that the H-passivated wafer are exposed to air before being placed in an inert environment for the subsequent process step (epi, poly silicon, metal, ion implantation etc.). It can be seen in FIGURE 1 how native oxide regrowth occurs after HF treatment in air and UPW vs. exposure time [1].

Screen Shot 2017-12-06 at 12.26.01 PM

A similar DO vs. surface oxide and carbon relationship is also verified using encapsulated SIMS. This method uses dynamic SIMS to measure the amount of O, C that are trapped at the epi layer/silicon wafer interface. This has been a widely used characterization method to assess a pre-low temperature epi surface prepa- ration process’ hydrogen surface passivation quality since the early 90s. The typical epi cap is ~80-150nm and is deposited using a 650°C SiH4 source deposition process. The objective is to be able to minimize the thermal budget of the pre-deposition bake step which is required to remove any surface oxides and organics to allow perfect epitaxial deposition with no contami- nants or defects at the interface.

FIGURE 2 demonstrates how the encapsulated SIMS interface O (areal oxide density, AOD) using a 650°C SiH4 no bake Si deposition process is strongly dependent on the DO concentration. Three samples are depicted with different surface preparation conditions, a reference wafer with no surface preparation, a wafer dHF wet processedwith the UPW DO ~ 1ppb, and a wafer dHF wet processed with the DO ~0.1 ppb.

Screen Shot 2017-12-06 at 12.26.31 PM

It can be seen in FIGURE 3 how applying a 700C/80T/60s bake before a 650C Si deposition process with the UPW DO at 0.1ppb yields non-detectable O and C. This SIMS data info is relatively old (2010) but is still good for reference. The current APET TeraDox wet process capability can provide non-detectable O and C without a bake before the 650°C Si deposition process.

Screen Shot 2017-12-06 at 12.26.46 PM

As mentioned earlier, undesirable native oxide thickness increases with queue time on H-passivated Si, SiGe and Ge surfaces. So, it is important to minimize the Q-time between the H-passivation process and the subsequent process step, but the quality and stability of the H-passivation does need to accommodate practical queue times in a manufacturing environment. The H-passivation from the APET TeraDox process has proven to be stable enough for up to at least 8-hour Q-times for most low temperature process applications, which makes it suitable for most semiconductor device manufacturing facilities.

Aside from the low surface oxygen benefit from having ultra-low DO in this process there are other very important benefits to this as well. Having ultra-low DO prevents water marks, microroughness (faceting), bacterial contamination and material consumption. If there is no DO in the UPW or the etching chemistry then there is no competing mechanism to simultaneously oxidize and etch the semiconductor material during the oxide etch and insitu-rinse steps. If the surface is being oxidized/etched then orientation selective faceting will occur. Faceting leads to gener- ation a mix of mono-, di- and tri- hydride terminations on the different orientations of the semiconductor surface. An example is silicon (100), which if it is kept atomically smooth after the oxide is removed by HF, the surface will be dominated by di-hydride terminations. If the surface is faceted it will contain lower energy mono-hydride terminations. Higher energy hydride bonds lead to better surface stability while the lower energy hydride bonds make the surface less stable and will re-oxidize faster with Q-time.

So in general, the pristineness and the atomic smoothness of the semiconductor surface are what dictates the quality and stability of the H-passivating surface preparation process.

While the TeraDox process performance has continued to improve with the new innovations, the capabilities have surpassed the detection limits of conven- tional measurement methods like encapsulated SIMS characterization. Encapsulated SIMS also has a lot of drawbacks and limitations which make it an impractical process monitoring method in manufacturing facil- ities. The need to have a more sensitive measurement method that can measure “as processed” surfaces in a fast, real time and non-destructive manner had become an urgent requirement.

There are a variety of very good electrical and optical measurement methods that have been in use for many years, but most of them do not provide surface specific information directly. Surface parameters such as surface recombination velocity and lifetime (SRV and Ts) can be calculated relatively accurately using multiple step procedures by measurement methods such as uPCD, QSS-PC, PL and SPV. SRV (surface recombination velocity) and Ts (surface recombination lifetime) are extremely sensitive to surface contamination such as C, O metals and dopants as well as micro- roughness. This diverse sensitivity make it ideal for assessing surface preparation methods.

Until recently, only one measurement technique has been found that can measure the SRV and Teff (effective lifetime) of the surface directly and quickly on as processed H-passivated wafers. While doing a lot of research for the ideal measurement method to pair with the APET TeraDox H-passivation process, it was discovered that an enhanced version of the CADIPT department at the University of Toronto’s PCR-LIC technology, called Quantitative Lock-in Carrierog- raphy and Imaging (Q-LIC), could have the unique and enabling capabilities needed for this application. After completing an array of screening and optimization testing over the course of 8 months, the results have validated Q-LIC as an ideal measurement method for “as processed” H-passivated surfaces. In FIGURE 4, the plot demonstrates the SRV vs Q-time for four different wet cleans and an unprocessed control. The data shows strong evidence of the differentiation between different H-passivation methods (process and equipment), the level of DO in the wet process chemistry, and the dynamically changing surface state over time.

FIGURE 4. Q-LIC SRV measurements vs Q-time for four different HF last wet processes.

FIGURE 4. Q-LIC SRV measurements vs Q-time for four different HF last wet processes.

APET currently has five patents, related to this technology, integrated on the commercially available TeraDox wet process equipment, four of which include the use of vacuum/N2 sweep degassing with membrane contactors for both the UPW and chemical degassing.

The UPW degassing is done in a separate stand-alone module (called the APET Dox unit) that treats up to 60 lpm of UPW before going to the main unit. All Dox units are guaranteed to have DO < 1 ppb, but all of the units in use to date achieve < 200 ppt. The most recently installed Dox unit system has a base DO level of ~30-40 ppt. Aside from the importance of PPT level degassing of the UPW much attention has also been given towards the design and materials used in the entire TeraDox system to prevent gas permeation into the UPW supply and the process chemistry to achieve optimum H-passivation. The most recent TeraDox related patent that was issued to APET was for chemical degassing. The degassing of the HF and HCl are typically overlooked in this application. Typically, HF comes in ~48% and HCl in ~37% concentrations with the balance of these supplied mixtures is in DO saturated water. So even diluted etching chemistries of up to 400 (UPW) :1 (chemical) ratios will typically still produce a composite DO of > 3ppb in the process vessel, even if the UPW supply is degassed to 0 ppt. Having the unique chemical degassing capability to < 1ppb DO significant improves the overall performance of the H-passivation process. The chemical degassing apparatus is integrated into the HF and HCl chemical delivery lines inside the TeraDox system’s main unit.

In summary, APET has developed and commercialized a unique and enabling wet surface preparation technology, the TeraDox process and equipment, that can produce pristine and stable hydrogen passivated semiconductor surfaces. While there are several critical factors and innovations that enable the TeraDox’s unique process performance capabilities, the fully integrated “dry in/dry out” system design and the unique PPT level degassing of the process chemistries are the most facili- tating features on the TeraDox system.

Acknowledgement

A special thanks to Dr. Andreas Mandelis and his staff at the University of Toronto for their support in optimizing their Q-LIC system to provide data for this paper as well as demonstrating a suitable measurement method for the “as processed” H-passivation application.

References

1. M. Morita et al, J. Appl. Phys. 88 (3), 1 (1990)
2. A. Philipossian, J. Electrochem. Soc. 139 No. 10, 2956 (1992)
3. F. H. Li, M. K. Balazs, and S. Anderson, J. Electrochem. Soc. 152,
G669 (2005)

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