Chipworks


Apple Watch and ASE Start New Era in SiP

By Dick James, Senior Technology Analyst, Chipworks

Back in April the Apple watch appeared in our labs, and of course we pulled it apart to see its contents. That set us some challenges, since inside the case we have the S1 “chip” (as Jony Ive called it in the launch last year). As you can see, it occupies most of the space inside the case, so it’s a pretty large chip; normally only the likes of IBM or Nvidia make chips this large.

01_1

 

Actually, we knew that there had to be multiple chips inside the S1, because we did a pseudo-teardown last year, based on Apple’s promo video at the time. It turns out that the S1 is actually an assembly of chips on a dedicated printed circuit board (PCB) substrate, with over 30 chips plus many passive components. So it is more accurately described as a System-in Package (SiP).

This was confirmed when we took the S1 out of the case and x-rayed it;

02_0

03_0

 

And we identified many of them;

04_0

 

This gave us the teardown information that we needed to find what chips were used, but the S1 is so different from any of the other wearables that we have looked at, that we had to go in and see how it was put together. So cut it in two and then onto the polishing wheel, and we get an idea of what Apple’s assembly house has done for them.

Actually, we did two cross-sections along the lines shown here;

05_0

 

This is section P1AS2;

07

On the left is the Dialog PMU; in the centre is the Apple APU (APL0778), with an Elpida DRAM co-packaged; and at the right is the Sandisk 64-Gb flash, including the controller chip and a spacer die. There seemed to be a wide-spread assumption that the APL0778 would be in a Package-on-Package (PoP) stack with the memory, as in the iPhones, but here it is in a straight-forward two-die stacked package.

If we look closer, we can see that the S1 uses conventional assembly techniques, but once all the components are on the 4-layer PCB, the whole thing has been over-molded with more molding compound, and then plated with metal to give the stainless-steel looking finish. A close-up of the right edge shows what I mean;

08

 

There are two 32-Gb flash dies in a conventional package with its own substrate, which is flip-bonded onto the PCB, covered with the SiP over-molding, and the exterior is metallized, giving the silver finish.

Section P1AS1 has the Broadcom BCM4334 in the centre, and the AMS NFC booster chip on the right. At left is a co-axial RF test socket.

10

Again, if we look closely, we can see that underfill has been used across the whole PCB before the over-molding was performed. Another feature of note is the I-shaped EMI shielding on the right of the BCM die, molded into the SiP – this is the first time we have seen this in any sort of package. In the x-ray image above, it surrounds the BCM chip, separating it from the other components. Here we are in close-up;

11

 

In effect the complete S1 assembly has EMI shielding since (with the exception of the accelerometer/gyro) the whole thing has a metal coat, mostly copper with a skin of iron/chromium. Such a coating will also inhibit moisture ingress, a good thing since I’ve heard tales of folks showering while wearing a Watch, and wrists can get a bit sweaty anyway.

A big question for us is – who supplied such an innovative package? Press commentary has identified the provider as ASE (Advanced Semiconductor Engineering Inc.) of Taiwan; and I presented at an IMAPS wearables workshop back in June, and when I got to the Watch analysis the attendees from ASE shared a few knowing looks.

The last quarterly analyst call from ASE also included this graphic, which details quite nicely the SiP concept, and includes details such as the EMI shielding:

final

 

ASE has also had more revenue from SiP this quarter, “In terms of overall, the SiP revenue accounted for about 22% in the second quarter, up from 15 a quarter ago because of the EMS SiP product ramp up.” Interestingly, they are also running below break-even on the SiP product (In response to a question as to whether all SiP projects are losing money, or just the one; “Thank God it is. It’s only this particular project that is running below break-even. Other things are moving very nicely.”).

Given these comments, I’m inclined to believe the press on this one – ASE is the supplier.

Another nugget comes from perusing the transcript of the call – “What kind of application and what kind of customers you are working with for the new SiP projects?

Tien Wu replied, “I don’t think I’d comment specifically but I’m pretty sure you will find some new products that have come out pretty soon. Sorry.”

He also noted, “We promise each other will never come out specific customers. So I will give you a non-qualifying, non-specific answer. We are expanding the SiP coverage to the cellphone, to the tablet in that particular arena. Hopefully, we can report more revenue, more penetration.”

I take that to mean that we may well see this style of SiP in the new iPhone and iPad later this year – more fun!

 

The Confab – Semi Industry is Now Mature

By Dick James, Senior Technology Analyst, Chipworks

The Confab started on Tuesday last week, an industry get-together organised by Solid State Technology (part of Extension Media), which they promote it as the “Semiconductor Manufacturing & Design Industry’s Premier Conference and Networking Event”.

The conference portion started with an afternoon panel session, “Exploring the Edges of Semiconductor Technology and Business”; I had the pleasure of kicking it off with a presentation on the state of the art in the business, as seen by Chipworks, then we got together on the podium for the panel part of the discussion.

Pete Singer moderated, and the other panelists were my co-blogger Phil Garrou, and Gopal Rao, ex-Intel and now an independent consultant. Pete had a set of pre-prepared questions on where we thought the business was going, the progress of 3DIC, and what we thought the impact of IoT (internet of things) might be.

Left to right: Phil Garrou, Dick James, Gopal Rao

Left to right: Phil Garrou, Dick James, Gopal Rao

We did our best to answer these and other questions from the floor, but Phil brought up a point that resonated with me; in the major segments of our industry we’re now down to three players, and that’s a sign that those segments have probably consolidated as much as they can. In the same way the auto industry has consisted of three significant players in each continental market (three in North America, three in Europe, etc). It’s a bit of an arm-wavy argument, but I think that it’s at least arguable.

So in DRAM we have Samsung, Micron, and SK-Hynix; in flash we have Samsung, Micron, SK-Hynix, and Toshiba/Sandisk: and in leading-edge logic we have Samsung+GLOBALFOUNDRIES, Intel, and TSMC.

Subramani Kengeri from GLOBALFOUNDRIES gave a good illustration of this a couple of years ago in an ASMC keynote speech:

Capture

 

And Tom Caulfield (also GLOBALFOUNDRIES) followed it up at this year’s ASMC, specifically in the DRAM space:

Capture2

 

This is a point also made by Bill McClean of ICInsights in recent years, but he continues the logic to argue that now we are a mature industry, the business will tend to follow the world economic cycle rather than the capacity-based boom/bust cycles that we have seen in the first few decades.

Which makes sense from the mile-high perspective – we have all seen the changes in the customer base from the defence and computer industries, through the PC era, to a largely consumer-driven set of products – Apple is now the largest buyer of silicon chips in the world, after all.

Bill bracketed the Confab sessions neatly by giving the final presentation – “Are IC industry cycles dead or just sleeping?” His conclusion was that they are likely sleeping, but the trigger has changed from chip-making overcapacity or shortage, to whether world GDP goes positive or negative. To support that contention, he showed the correlation between worldwide GDP and IC market growth is now better than 0.9, compared with 0.35 back in the eighties.

Capture3

 

This trend is likely a result of the consolidation of companies that we’ve seen and will continue to see, combined with the move to fabless and fab-lite, and its consequent tighter control over Capex; and, last but not least, the lack of disruptive new entrants to build mega-fabs and add over-capacity. China has had its play, India does not seem to want to get into that end of the business, and the Russian economy doesn’t seem to be up to it.

Capture4

 

So, while we will see periods of growth and recession as always happens, likely amplified for our business since we are now so tied to consumer cycles, hopefully we won’t see the disruptive/destructive ups and downs that old-stagers like me have seen every three – five years in the last four and a half decades.

Having said that, there will be challenges, and it’s hard to see beyond 2020. We are now in the 14nm era in logic processes, and in five years (assuming a two-three year gap between generations) we will be ramping up seven-nm and heading for five.

In DRAM, Samsung has three 1x-nm nodes in their roadmap, possibly spread over five years, and flash is already at 14 – 16nm and moving to vertical – but how long will that last? Theoretically, I guess v-NAND could shrink from its current ~40nm node down to ~15nm, with more layers stacked together.

(That gives us the prospect of multi-Terabits on a single die, and I guess server farms would likely love such a product. On the consumer side, it does make me wonder if there is actually a market for (say) a 16-TB MicroSD card. On the whole, it starts to make my brain hurt.)

Those thoughts left me leaving the Confab actually wondering where these mainstream products are going to be in the early twenties, or if the technology is going to run out of steam. I know we’ve had these thoughts before, mostly due to mis-perceived lithography limits, but now we’re getting to the point where there may not be enough atoms or electrons to do what we want to do using current techniques.

Of course the research consortia are busy looking at ways of getting past this apparent impasse, it’s just that there seem to be quite a few options and no clear winner at the moment. And all the above doesn’t even consider the possible introduction of EUV and/or 450mm wafers.

Time will tell, and I may be retired by then, but we do live in interesting times, and it’s not going to change..

Apple Watch Launch Confirms WiFi and NFC Inside

By Dick James, Senior Technology Analyst, Chipworks
Today (April 10) is the day that the Apple Watch becomes available for order, and of course we will be buying some to see what’s inside. We won’t be going for the gold Edition model, even so some of us here would like to; the Sport version should be quite good enough.
At the Apple event back on March 9 it was almost a case of last and least for the Apple Watch, after listening through the ResearchKit and new MacBook launches, and more Apple Pay demos. The Watch presentation was almost a case of déjà vu, since we got most of the details last year in the announcement last September.
The one new technical detail that I did pick up on was that the use of WiFi was confirmed – there was no mention of that last year (time 74.00 in the March 9 video). There was also much emphasis on the ability to use Apple Pay and make calls through the Watch, so we know that there are microphones in there, and it has NFC (near-field communications) capability, but we knew that after the initial launch last year.
The WiFi news was interesting to us, since we did a pseudo-teardown back then, based on Apple’s promo video, and we came to the conclusion that the Broadcom BCM4334 was in the Watch. But no mention of WiFi – what gives? I guess they just forgot, and even in the new launch it was just a passing reference.
We identified the BCM4334 from a layout image of the board inside the Watch that we took from a screen capture of the video, and the characteristic footprint of a flip-chip component.

Screen shot of PCB from Apple Watch – source: Apple film “Introducing Apple Watch”

Broadcom BCM4334 die and position on Apple Watch PCB

 

According to Broadcom, “The BCM4334 is a single-chip dual-band combo device supporting 802.11n, bluetooth 4.0+HS & FM receiver. It provides a complete wireless connectivity system with ultra-low power consumption for mass market smartphone devices. Using advanced design techniques and 40nm process technology to reduce active and idle power, the BCM4334 is designed to address the needs of highly mobile devices that require minimal power consumption and compact size while delivering dual-band Wi-Fi connectivity.”
So we have WiFi confirmed! In the meantime we’ve been looking at that board a little more, and we have also confirmed that the NFC and NFC booster chips used in the iPhone 6 and 6 Plus are also present.
Again, we looked at the footprints on the board – nothing quite as characteristic as the Broadcom chip, but knowing the size of the chip package and the solder ball array density gives us a good clue. And knowing the size of the BCM4334, we can work out the sizes of the other chips on the board.
In the iPhone 6 the NFC controller was a NXP 65V10, which contained the PN548 die, and an AMS AS3923 NFC power booster; so it’s at least a possibility that Apple will be using them in the Watch.
Below is the AS3923 from the iPhone, showing the 5 x 4 solder ball grid on the bottom of the part. Like the Broadcom chip, it is also a flip-chip-on-board (FCOB), so the die size will be characteristic, and while a 5 x 4 grid is certainly not unique, the combination of the two gives us reasonable confidence that a matching footprint on the Watch board indicates the presence of an AS3923.
Top and bottom images of AMS AS3923
Similarly with the NXP 65V10:
Top and bottom images of NXP 65V10 
Here we have a 7 x 7 array, but it and the die size coincide with a footprint on the PCB.
Lastly, a business contact pointed out that the motion sensing is likely done by the same Invensense sensor that was used in the iPhones, the MP67B (probably the MPU6700), and when we looked, again the size and solder pads match. We wrote about this after the iPhone analysis,and in its lowest power mode, it can draw less than 10 µA.

Top and bottom images of Invensense MP67B

Putting these three together, we see below:

PCB from Apple Watch showing Invensense, AMS, and NXP die positions

Come April 24 we will know what else is in there, as you can see that board is quite packed. In the meantime, we’ll be looking for some more recognizable components.

 

Samsung’s FinFETs ARE in the Galaxy S6!

By Dick James, Senior Technology Analyst, Chipworks

The much anticipated Samsung Galaxy S6 made an early appearance in our teardown labs last week,  thanks to the diligent skills of our trusted logistics guru. We got our hands on the 4G+ version, the SM-G920I, with what Samsung claims is the world’s first octa-core 64 bit operating system. There is a wide array of industry buzz surrounding this flagship smartphone, but from my process-oriented point of view the focal point has to be on the Exynos 7420 application processor.

Samsung Galaxy S6 Teardown
Galaxy S6 Motherboard

Samsung Exynos 7420 Application Processor

The Samsung Exynos 7420 application processor is reportedly fabbed in Samsung’s 14 nm FinFET process. This is what Samsung has shown so far.

Which is not exactly specific! To start with, here’s the package marking of the package-on-package:

The layout of this is quite unusual – normally the memory marking (SEC 507 etc.) is in lines of text above the APU marking (7420 etc.), not in a diagonally opposed block. Which leads me into the speculation that maybe the 7420 is out of GLOBALFOUNDRIES, rather than a Samsung fab in Korea or Texas. Could ALB be short for Albany (NY)? Is the G in the lot code short for GLOBALFOUNDRIES? That all seems rather unlikely, but if Samsung wants to switch on the volume quickly in anticipation of huge volumes for the S6, what better way than to use three fabs? They did sound very confident in their last quarterly analyst call, saying that they expect 14-nm to be 30% of the LSI line capacity by year end. And there are lots of rumours about Qualcomm using the Samsung 14-nm process.

The die photograph and the die mark confirm the use of the Exynos 7420:

The functional die size is ~78 mm2, which compares well with the ~118.3 mm^2 of the Snapdragon chip used in the Galaxy S5, and the 113 mm^2 size of the 20-nm Exynos 5433. If the 7420 was a straight shrink of the 5433, we’d expect it to be 55 – 60 mm^2, but the back-end metallization stack is reported to be similar to the 20-nm planar process, so a full 50% shrink is unlikely (and the analog regions never shrink as well as digital anyway). We’ll have to wait until we see the floorplan to see how much functionality the two parts have in common.

Our guys in the lab made their usual exceptional effort in enabling us to see what the process looks like – within a few hours of getting the phone in-house, we have a decapsulated part and a cross-sectional sample under the microscope.

The Exynos 7420 uses 11 layers of metal, as you can see from the die seal cross-section above. Now let’s look at the transistors:

And we do have finFETs! This section is parallel to the fins, and across the gates. The bottoms of the contacts approximately indicate the top edge of the fin, and we are seeing the gates wrapped over and further down the sidewalls of the fin than the contacts appear to go. We will need another section orthogonal to this one to see if we have the type of epi growth in the source-drains that Intel uses.

This makes Samsung the second in line to get finFETs into volume production; they have successfully taken their 20-nm, first-generation, gate-last, high-k, metal-gate stack and adapted it to a first generation fin structure. We will need more detailed images to see whether the fins have vertical or sloped sidewalls, and how close to the Intel model they are, but those will come in the fullness of time when we have completed our full analysis and published our report.

Meanwhile, keep an eye on the blog!

IEDM – Monday was FinFET Day

By Dick James, Senior Analyst, Chipworks

In my conference preview blog last week, I mentioned that session 3 on the Monday afternoon would be a hot session, with three finFET papers, by TSMC, Intel, and IBM. I was right – even though they were given in the Grand Ballroom, it was full.

Paper 3.1 from TSMC disclosed what looks like their 16FF+ 16nm finFET technology, advanced from the 16FF reported last year – although they don’t actually call it that in the paper. A 15% speed boost and 30% power reduction is claimed, or 40% speed gain and 60% power saving compared to the 20nm process.

Gossip in the industry has it that 16FF was not advanced enough for TSMC’s customers, so they did some transistor engineering and cranked up the performance; 16FF is not even mentioned on the website these days, and 16FF+ is now in risk production, with endorsements by Avago, Freescale, LG Electronics, MediaTek, Nvidia, Renesas and Xilinx.

The 48nm fin pitch and 90nm contacted gate pitch announced last year were maintained, as is the 1x metal pitch of 64nm. This level uses “advanced patterning scheme” – presumably self-aligned double patterning (SADP), whereas the other 80/90 nm pitch metals are done with single patterning. The low-k dielectric stack has been optimized relative to the 16FF process to give almost 10% capacitance  improvement, and  they have also added a planar high-k MIM capacitor (>15 fF/um2) for on-chip noise reduction.

At the transistor level, we have a dual-gate oxide process, replacement metal gate (gate-last), dual epitaxial raised source/drains, and tungsten local interconnect – but NO PICTURES! Lots of plots, but no transistor images, as in last year’s 16FF paper, and we were out of luck in the live presentation as well.

So we still have no idea of what the TSMC finFETs will look like. I guess that’s good for me and Chipworks, since we’ll have to wait until they actually show up in the real world sometime next year.

Intel gave a late news paper (3.7) describing their 14nm finFET (note – finFET, not trigate) process at 4.05 pm. Being late news, there were only 15 minutes for Sanjay Natarajan to describe what looks like a technology that is distinctly changed from the 22nm process. AND there were images!

3.7-1

 

As announced back in August, fin pitch is reduced to 42nm, contacted gate pitch to 70nm, and 1x metal to 52nm, and we confirmed these in our blog on the Broadwell chip that we pulled out of a Panasonic laptop. In addition to the fins, the gates and the minimum metal levels use SADP, making for complex front-end lithography.

3.7-2

The fins have been modified from the 22nm process to have a more vertical profile, slimmed down to 8nm wide, and Intel also claims a “novel sub-fin doping technique” using “solid-source doping to enable better optimization of punch-through stopper dopants.” Sanjay’s presentation revealed that the solid-source doping uses a doped glass; now it’s down to us to work out when and where it’s used for punch-through inhibition. Idsat is claimed to improve by 15% for NMOS and 41% for PMOS over 22nm, and Idlin by 30% for NMOS and 38% for PMOS.

Changes have also been made to the back end – low-k dielectrics are used in the first eight levels, and significantly we see the first use of air-gaps in the M4 and M6 levels (80 and 160nm pitch).  This is Intel’s SEM image from the paper:

3.7-3

 

And here’s a TEM image from our analysis:

Intel airgaps2

can see from the spacing of the gaps and the profile of the barrier layer over the copper that a patterned approach has been taken, as described in the IITC 2010 paper [1], using a mask step after the formation of the metal seal layer.

Intel likes to point out their history – this is the second generation finFET, fourth generation HKMG, and sixth generation strained silicon; will their 10nm be the third, fifth, and seventh generations?

I’m now inclined to think so, since at an Applied Materials event in the evening, when asked about the delay in the 14nm launch, Mark Bohr was heard to say “We won’t have similar problems at 10nm”. Mark does not make such comments lightly, so to me that implies two things – the 10nm process is pretty well locked down already, and it’s unlikely that there are huge structural changes from the 14nm generation. Indeed, the aggressive shrink from 22nm to 14nm puts them well on the way to the predicted 10-nm feature sizes.

Immediately after Intel’s talk IBM had their 15 minutes of IEDM advanced CMOS fame, describing their 14nm technology. This has their fourth generation embedded DRAM, but is the first-gen finFET, and the first-gen gate-last process (and I’ve lost count of the SOI generations).

IBM claims a “unique dual workfunction process applied to both NFETs and PFETs” and sub-20nm gate lengths, which will be the smallest we’ve seen if we ever get a sample. Being IBM, the intended product will be over 600 mm2 and have 15 metal levels, presumably their Power9 server chip.

Fin pitch is the same as Intel at 42nm, but contacted gate pitch is 80nm, and 1x metal is 64nm. Here the fins are completely isolated since they are on the buried oxide, so no punch-through implants are needed at the base of the fin as on a bulk silicon substrate.

We do have pictures – these are really fuzzy, but we can see the gate wrapped over the fin with slightly raised source/drains on either side, and some nice facets on the source/drain epi.

During the presentation there were (of course) no details of the work-function materials, but it was stated that two masks were used to make the dual work-function structure; so presumably two slightly different material sets for the different work-functions. Another tidbit was that the pass-gate transistors

IBM3-8-1

 

In the e-DRAM had a different Vt than the logic transistors, but not achieved by a workfunction change.

I’d missed it, but the IBM alliance gave a paper at the VLSI conference back in June [2], where they describe a 10nm finFET process; this look likes the same process, backed off to 14nm and with the e-DRAM added.

The e-DRAM introduces some challenges in connecting the trench capacitor plate to the fin of the pass gate. In the planar 22nm version there is a polySi strap from the polySi in the trench to the SOI on the buried oxide; in the finFET design the polySi strap is still used, but it is formed as a plug on the trench fill connecting to the SOI layer before fin definition, and the plug is etched into a fin during the fin etch. The epi module has been tuned to minimise the strap resistance and therefore the effect on access time.

Cell size of the eDRAM is now 0.0174 μm2; and if the trench capacitors are coupled together without the select gates, they can provide on-chip decoupling capacitors with a value of 450 fF/um2.

IBM3-8-2

 

IBM3-8-3

 

In the back-end IBM has their fifteen layers of metal ranging from 1x – 40x, and the section shows that the 40x is seriously thick, to take the power needed to run a chip this size!

IBM3-8-4

 

That made for an eventful afternoon, with a bit of a disappointment from TSMC; we’ll look forward to seeing both their finFET and the Power9 next year. Of course we have a suite of reports on the Intel Broadwell, for those who want a detailed analysis of the part!

References

[1]   H.J. Yoo et al., “Demonstration of a reliable high-performance and yielding Air gap interconnect process”, IITC 2010, pp. 1-3

[2]   K-I Seo et al., “A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI”, VLSI Tech 14, pp. 12-13

IEDM 2014 Preview

By Dick James, Chipworks

Later this month, the good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2014 IEEE International Electron Devices Meeting.  To quote the conference web front page, IEDM is “the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation. The conference scope not only encompasses devices in silicon, compound and organic semiconductors, but also in emerging material systems. IEDM is truly an international conference, with strong representation from speakers from around the globe.”

That’s a pretty broad range of topics, but from my perspective at Chipworks, focused on the analysis of chips that have made it to production, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years.

In the last few days I’ve gone through the advance program, and here’s my look at what’s coming up, in more or less chronological order.  As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.

Saturday/Sunday

Again this year the conference starts on the Saturday afternoon, with a set of six 90-minute tutorials on a range of leading-edge topics:

The first three are from 2.45 – 4.15, and the remainder from 4.30 – 6.00.  This year I hope to make it to my old friend Wilfried Vandervorst’s session on characterisation, and possibly the other imec tutorial on memories at 4.30.

Wilfried gave an impressive talk at the imec symposium at Semicon West, and this time he has an hour and a half instead of 45 minutes, so hopefully a good bit more detail on what we can see, now that we are counting atoms in transistor analysis.

On Sunday December 14th, we start with the short courses, Challenges of 7nm CMOS Technologies” and “3D System Integration Technology. Last year the short course was “Challenges of 10nm and 7nm CMOS Technologies”, so I guess we’ve moved on a bit; though I still need convincing that the 10-nm process architectures are locked down as yet.

Hidenobu Fukutome of Samsung has organised the former, and we have some impressive speakers – Greg Yeric, Senior Principal Design Engineer of ARM, (Circuit application requirements), Peide Ye, Purdue University (Device challenges), Guido Groeseneken, KU Leuven & imec, (Reliability challenges), Eric Karl, Intel, (On-die memory challenges), and Tsutomu Tezuka, Advanced LSI Technology Laboratory, Toshiba (Process and integration challenges). With 14-nm product on the market now, we need to look ahead, so this is appropriate – on the Intel clock, 7-nm is only four – five years away!

It now seems that 10-nm will be silicon-based, so we’ll see what the guys predict for 7-nm; new channel materials, nanowire transistors, and how will they integrate into a manufacturable process? What will be the effects on the performance of the basic logic blocks? What will device reliability be like with the potential new materials/structures? Hopefully we’ll find out here!

Eric Beyne of imec has set up the other short course; 3D is a very hot topic these days, both finFET and die stacking – here we are talking about die stacking.

Denis Dutoit of Cea-Leti looks at 3D System Design – Challenges for 3D Integration; I have the distinct impression that the manufacturing technology is in place, but design and test still have a way to go.

Next up is Kangwook Lee, Tohoku U, on Enabling Technologies: TSV Technology; again TSV technology is being promoted as here by both foundries and OSATs, and some products such as the Xilinx 2.5D FPGAs are out there, and stacked memories such as the Hybrid Memory Cube are sampling.

After lunch we have 3D evangelist extraordinaire Subu Iyer from IBM, talking about Enabling technologies: 3D integration for the Memory subsystem. IBM has been embedding DRAM into their products for several generations now, and as noted above, we are starting to see 3D-packaged memory come on to the market.

Wafer-to-wafer bonding is an essential part of 3D stacking, and that’s the topic of James Lu from Rensselaer Polytechnic. The last session is on 3D Reliability and Impact of 3D Integration on Devices, with Kristof Croes of imec discussing the device effects of the additional processing needed to make a 3D stack.

So some good solid stuff – although the courses make a long Sunday, from 9 a.m. to 5.30 p.m., but it’s worth sticking around to the end.

Sunday evening has some extra sessions; Sematech is holding a session on “Materials & Technologies for Beyond CMOS” at an as-yet unnamed location; and Leti will host a workshop on their “vision for silicon nano-technologies in the next 10 years” from 5.30 – 8.30 pm at the Nikko Hotel, across the street from the Hilton.

Monday

Monday morning we have the plenary session, with three pertinent talks on the challenges of contemporary electronics:

  • SiC MOSFET Development for Industrial Markets, John Palmour, Cree Inc. – broadening the range of uses for silicon carbide?
  • Are 3D atomic printers around the corner? Enrico Prati, CNR IMM (Italy’s Institute for Microelectronics and Microsystems) – now that 3D printers are becoming consumer goods, can we push the idea into the atomic scale? That sounds like the potential for everything from drugs design to the ultimate version of Moore’s law..
  • Research into ADAS with Driving Intelligence for Future Innovation, Hideo Inoue, Toyota – Automated Driver Assistance Systems; moving towards the self-driving car?

After lunch we have seven parallel sessions coming up!

Session 2 is a focus session on power devices, with a kick-off paper by John Baliga of NCSU, on the Social Impact of Power Semiconductor Devices (2.1). John invented the IGBT in his time at GE back in the 80’s, and claims that the technology has reduced global carbon dioxide emissions by 75 trillion pounds over the last 30 years. He speculates that this can only increase with the introduction of new power devices. Papers 2.32.5 and 2.7 look like reviews of high-power switch technologies, and Si-, SiC and GaN-based power devices, respectively, while 2.2 and 2.6 look at specific SiC JFET and GaN HEMT devices.

Session 3 is the hot Advanced CMOS Technology group of papers with late news additions by Intel (3.7) and IBM (3.8), both on 14-nm finFET technologies, which even triggered their own press release.

The Intel finFET (note – not trigate!) device features “a novel subfin doping technique” to minimise fin doping and leakage under the fins, and air-gaps in two metallisation levels. This is the first use of air-gaps in a production logic part that I know of; we’ve seen them in memory chips for a while. Intel had a persuasive paper on this at the 2010 IITC conference [1], and I was wondering if we would see implementation at this node.

If you hunt hard in Intel’s August 14-nm announcement, you can find the air-gaps in the M5 level:

Intel airgaps1

 

And we did find them in the M5 and M7 levels, but I will leave any detailed comment until a later blog. The IITC paper [1] speaks of using a mask step to define specific air-gap locations, and we can confirm that masking has indeed been used to define specific locations.

Now that we are analysing the Intel part, it would be remiss of me not to show an early shot of the fins, and they are clearly different from the 22-nm variety. There has been an obvious reduction in the width of the fin from its initial etched dimension, and it is tempting from this image to say that the NMOS fin is wider than the PMOS, but again more thorough discussion will have to wait.

Intel fins

IBM’s finFET is on SOI (of course, this is IBM!) and has a “unique dual workfunction process” which allows multi-Vt versions of both NMOS and PMOS, and claims sub-20 nm gate lengths. The process also includes fifteen metal layers and the latest version of their e-DRAM technology.

With all the Intel/IBM hype, I have become out of order here, because paper 3.1 from TSMC discloses what looks like their 16FF+ 16-nm finFET technology, advanced from the 16FF reported last year. A 15% speed boost and 30% power reduction is claimed, or 40% speed gain and 60% power saving compared to the 20-nm process.

Gossip in the industry has it that 16FF was not advanced enough for TSMC’s customers, so they did some transistor engineering and cranked up the performance; 16FF is not even mentioned on the website these days, and 16FF+ is now in risk production, with endorsements by Avago, Freescale, LG Electronics, MediaTek, Nvidia, Renesas and Xilinx, .

It will be interesting to see if any of the dimensions have changed from the 48 nm fin pitch and 90 nm contacted gate pitch announced last year. The metal stack is stated to be the same as the 20-nm planar process with a 1x pitch of 64 nm.

Paper 3.2 is from Avago, discussing Analog Circuit and Device Interaction in High-Speed SerDes Design in 16nm FinFet Process, and Renesas presents 3.3, on 16-nm 6T SRAM macros, both presumably TSMC’s process. 3.4 again looks at SRAM, but this time on STMicroelectronics’ 28-nm UTBB FDSOI process.

Next up is a couple of academic papers (3.5 & 3.6), discussing a 28-nm integrated RF power amplifier, and a 3D-stacked light harvester on a “epi-like Ge/Si monolithic 3D-IC with low-power logic/NVM circuits”.

3.7 and 3.8 are the Intel and IBM papers, and 3.9 is another late-news paper, from STMicroelectronics, but a change of pace from the finFETs – a 55-nm SiGe BiCMOS technology this time.

And by now it’s 5pm, the end of an intense afternoon!

In session 4, we take a look at Display and Imaging Systems. STMicroelectronics starts us off discussing MOS Capacitor Deep Trench Isolation for CMOS Image Sensors (4.1) in a joint talk with CNRS and CEA-LETI.

Goto 4.2

 

One of the goals in image sensors has to be integrating the A/D converters on each pixel, instead of at the edge of the pixel array, and 3D stacking comes to images sensors in paper 4.2 from NHK and U Tokyo; in which SOI wafers are direct bonded so as to provide each pixel with A/D conversion.

However, we won’t be seeing this in a phone anytime soon, as it is a proof-of-concept with 60-µm square pixels, as opposed to the 1-2 µm pixel pitch in most phone cameras.

NHK (jointly with Panasonic and U Hyogo) has another stacked sensor in 4.3, this time a selenium photodiode stacked on CMOS circuitry.

The remaining four papers are academic, covering far-infrared (4.4), a stacked SOI multi-band CCD (4.5), an embedded CCD in CMOS (4.6), and the display paper is 4.7, a solid-state incandescent device.

Session 5 covers Nano Device Technology – 2D Devices, a research session; 5.5 is a review of Nanophotonics with two-dimensional atomic crystals; the other papers all cover graphene devices (5.3, 5.4 and 5.6), black phosphorus (5.2), and molybdenum disulphide and tungsten diselenide (5.1, 5.7).

Resistive RAM is discussed in session 6. CEA-Leti has three papers in the afternoon,  (6.1, 6.3, 6.5) The first (joint with Altis Semi) looks at oxygen vacancies in doped oxide/Cu-based conductive bridge RAM (CBRAM), improving the Cu filament formation in the resistive layer; 6.3 is an invited paper that takes a higher level view of CBRAM and OxRAM devices in two different applications; and 6.5 is a detailed examination of CBRAM operation.

Micron and Sony get together to build a 27-nm 16Gb Cu-ReRAM part in 6.2, with a 1T 6F2 cell – definitely some DRAM technology showing up here, in the buried wordlines:

6.2 Zhurak

 

TSMC and National Tsing Hua U have a 28-nm BEOL RRAM in 6.4; Stanford U looks at thickness limits in HfO-based RRAM in 6.6; Crossbar (6.7) discusses crossbar RRAM arrays; and imec/KU Leuven finishes the session with a paper on a TiN/Si/TiN selection device for RRAM switching elements (6.8).

Modeling Simulation of Extremely Scaled Group IV and III-V FETs is the topic in session 7, looking way ahead.

In paper 7.1, imec and Synopsys look at the stress effects of 3D stacking on 7-nm devices(!); 7.2 examines mobility enhancement in sub-14nm FDSOI, by the CEA-Leti/STMicroelectronics/IMEP/IBM/SOITEC FDSOI crew; and transient electrothermal effects in nanoscale FETS are considered in 7.3., from Osaka U and Kobe U, and JST-CREST.

Victor Moroz (Synopsys) does a comparative analysis of 7-nm finFETs in different materials in 7.4 – this might be a follow-up of his talk at Semicon West back in July, in which he concluded that silicon is still the best channel material, at least for low-power mobile devices.

Samsung and Udine U also look at different material nFinFETs (7.5, 7.6), and Peking U discusses III-V ultra-thin body pMOSFETs in the last paper of the session (7.7).

NEMS (Nanoelectromechanical Systems) and Energy Harvesters are dealt with in Session 8 – six academic papers, ranging from graphene and Mo disulphide atomic-scale layers that vibrate at RF frequencies (8.1), to photoelectric hydrolysis on MIS photocathodes (8.6).

For those interested in energy storage, Intel have fabricated porous silicon capacitors (8.2) that can potentially be integrated on-die or onto solar cells, taking advantage of the extreme conformal deposition capabilities of atomic-layer deposition (ALD). The image below shows a top-down view of the porous silicon before and after ALD TiN deposition; the wall of the pore walls get thicker, but the pore structure doesn’t change. Capacitances of up to 3 milliFarads/cm2 are claimed.

8.2 Fig 5_Gardner

 

Then in the evening we have the conference reception at 6.30, through until 8 pm.

Tuesday

In the morning we have another seven parallel sessions, starting with session 9 on Advanced CMOS Devices for 10nm Node and Beyond, so another one I will definitely be targeting.

The first paper (9.1, from IBM/STMicroelectronics/SOITEC/CEA-Leti) is about strained 10-nm FDSOI devices, incorporating “a fully compressively strained 30% SiGe-on-insulator (SGOI) channel PFET on a thin (20nm) BOX substrate”; they also report ‘strain reversal’ in a PFET – is that so much strain that it reduces mobility? In their workshops at last year’s IEDM and Semicon West, CEA-Leti have been showing a roadmap that jumps from 28-nm to 14-nm and then 10-nm nodes – this looks like the first showing of the 10-nm technology.

That is followed (9.2) by an invited talk from Simon Deleonibus of CEA-Leti on how process technologies can move us towards the zero-power era(?).

Purdue U claims the First Experimental Demonstration of Ge CMOS Circuits (9.3) on a GeOI substrate, while TSMC details InAlP-capped Ge nFETs on Si and Ge substrates (9.4), and Ge n-finFETs on Si (9.5). Still in germanium, National Taiwan U talks Ge nanowire nFETs on SOI (9.6).

The last paper of the session (9.7) is from AIST in Japan on tunnel finFETS in a CMOS process.

Session 10 is a focus session on Novel Imagers and Specialty Imaging Applications, starting with an invited talk by Jiaju Ma (10.1) from the Thayer School of Engineering at Dartmouth, on the Quanta image sensor; as near as I can make out, this type of sensor scans the pixel array so fast that it effectively reads individual photoelectrons, and the image is formed by integrating x, y, and time.

Paper 10.2 from TU Delft discusses single-photon avalanche diodes (SPADs), which have enabled solid state range finding, fluorescence lifetime imaging, and time-of-flight positron emission tomography. The topic of 10.3 (Ritsumeikan U, TU Delft, Osaka U) is high-speed image sensors, aiming for one giga-frame per second!

Another invited talk is by Siemens (10.4), about organic photodetector imaging, and next  imec details a CMOS-compatible approach to hyper- and multispectral imaging (10.5).

In a different spin, Annette Grot of Pacific Biosciences (10.6) will discuss how high-resolution, low-noise and high-speed image sensors have enabled large amounts of DNA to be sequenced quickly and at reduced cost; and how further advances will keep on pushing productivity and cost reduction.

For the final talk, we go from chip-scale to huge – the large scale hybrid pixel detector systems used at the Large Hadron Collider experiments at CERN (10.8).

Session 11 is the second group of talks about power and compound semi technologies, this time on High Voltage and RF Devices. Five of the six papers are on GaN devices, and one (11.2) describes a diamond MOSFET good up to 400C. We have a new acronym in there – a SLCFET (Super-Lattice Castellated Field Effect Transistor), with a 3D castellated gate structure (11.5) – that should make for a couple of interesting slides!

Circuit/Device Variability and Integrated Passives Performance is the focus of session 12; the middle papers, 12.3 and 12.4 are the passives talks, on Ultra-High-Q Air-Core Slab Inductors (IBM), and Above CMOS Integrated High Quality Inductors for wireless power transmission (HONG Kong UST). The other discussions range from finFET simulations (12.1 and 12.2) through MTJs for random number generation (12.5), noise suppression by using dynamic threshold voltage MOSFETs (12.6), and finally a consideration by ARM of poly pitch co-optimization in standard cells below 28-nm (12.7).

We look ahead to TFETs and other Steep-Swing Devices in session 13. The first paper (UCal Berkeley, Toshiba) discusses a nano-mechanical relay (13.1), which inherently has zero off-state leakage and perfectly abrupt ON/OFF switching behavior, but also serious manufacturing challenges. 13.2 and 13.3 are TFET talks, the 13.4 topic is a Schottky-barrier Si FinFET, and 13.5 and 13.6 review piezoelectric negative differential capacitance effects and devices.

Advanced Memories and TSV are the subjects of session 14; the first four papers are more resistive RAM, from imec (14.1 and 14.2), Politecnico di Milano/Micron (14.3) and Politecnico di Milano/Adesto (14.4). Adesto is the only company I know actually selling CBRAM parts, although we haven’t had a chance to look at them yet.

14.5 is a follow-up paper looking at noise in Samsung’s V-NAND flash [2], and 14.6 is also a follow-up from IBM on mobile ion penetration from BEOL layers close to TSVs. IBM’s TSV process uses MEOL connection to the TSVs [3], so it’s feasible that there could be some cross-contamination. Tohoku U contributes the last discussion (14.7), testing polyimide TSV liners as a way of reducing the stress in the adjacent silicon.

More sensors and MEMS papers in session 15; the first three are from Tsinghua U, about different applications of graphene MEMS (15.2 also from Berkeley), and TSMC/U Illinois contribute 15.4, on an integrated 180-nm SOI-CMOS biosensor.

A*STAR in Singapore author the final two papers, but on very different topics. 15.5 is an optical biosensor with Ge photodetectors built in to the back end, and 15.6 details a MEMS-tunable laser combined with a photonic IC.

The speaker at the conference lunch will be T.J. Rodgers, founder, President and CEO of Cypress Semiconductor, a well-known voice in the business for decades. Given the recent news of the merger between Cypress and Spansion, he could be an illuminating speaker!

Session 16 focuses on Ge and SiGe Transistors, starting with an IBM/GLOBALFOUNDRIES report (16.1) on strained SiGe-OI finFETs with 50% Ge and fin width of 3.3 nm and gate length of ~16 nm; clearly aimed at the 10-nm node.

16.2 Fig4(combined)_Barraud-c

 

Looking a bit further into the future, CEA-Leti/STMicroelectronics/SOITEC (16.2) examine omega-gate CMOS nanowires, with strained SiGe-channel p-FETs and Si-channel n-FETs, integrated into a SOI-CMOS process. From the look of the pictures below they are using a gate-first approach, so there is still some life in that technology.

16.3 is another nanowire paper from National Tsing Hua U, this time with dopant-free Ge junctionless nanowire non-volatile memories as well as Si nanowire FETs; and 16.4 is a study of Ge quantum-well finFETs fabricated on a 300mm bulk Si substrate, from Penn and N. Carolina SUs with TSMC and Kurt Lesker Co.

Imec tries out replacement metal gates on Ge n-finFETs with raised NiSiGe source/drains in 16.5; AIST examines poly-Ge-OI junctionless p- and n-finFETs, fabbed by flash annealing in 16.6; and Purdue U (16.7) reports on GeOI CMOS devices with recessed S/D.

Session 17 looks at Trapping Mechanisms in AlGaN/GaN Transistors; definitely at the academic end of the scale for me, although the last paper, CMOS-Compatible GaN-on-Si Field-Effect Transistors for High Voltage Power Applications, by TSMC, seems a bit out of place (17.6).

Session 18 is the second one on circuit/device interaction, this time considering Analog and Mixed Signal Circuits. Xilinx studies the interaction between devices and analog circuits used in high-speed transceivers in both planar and FinFet processes in 18.1. Part of this will be using the TSMC 16-nm finFET process, we’ll see if it adds anything to their paper in session 3.

Broadcom looks at mismatch in HKMG transistors related to the layout, and finds sensitivity to top metal routing, in 18.2. GLOBALFOUNDRIES (18.3) looks at Analog and I/O Scaling in 10nm SoC Technology and Beyond; is it better to take an increasing proportion of the die for hard-to-shrink analog, or go with TSVs and multiple dies?

CEA-Leti has a pathfinding paper (18.4) reviewing RF front-end modules (FEMs) in the light of the increasing number of modes (GSM, WCDMA, LTE, etc) and frequency bands in mobile devices. There are now more than 40 bands worldwide, so we see multiple FEMs in the worldphones we take apart, and keeping costs down while enhancing capability is one of the understated challenges in the industry.

There is more RF from Mediatek in 18.5, this time examining Digitally-Intensive RF Transceivers in Highly Scaled CMOS; apparently, these days embedded intelligence is needed on-chip to reduce the sensitivity of circuit performance to device characteristics.

The last paper in the session (18.6) is from Keio U, discussing circuit/device interaction in the 3D context of inductive coupling between dies.

Session 19 is the third memory session, this time on MRAM, DRAM and NAND; the first three talks are focused on STT-MRAM, from imec (19.1), Hanyang U/Samsung (19.2), and LEAP (19.3). Then IBM updates on their embedded DRAM (19.4), now at the 22-nm node in their latest Power8 processor (which, being IBM, is ~650 sq. mm!).

TSMC discusses a new Self-Aligned Nitride non-volatile memory cell in 19.5, and Macronix updates us on their BE-SONOS charge-trapping NAND flash (19.6) in the last paper of the session.

Characterization and Reliability of Advanced Devices is the subject of Session 20; papers 20.1, 20.3, and 20.5 all deal with nanowire characterization; imec has two studies, on HKMG InGaAs finFETs (20.2), and ESD diodes in Si finFETS (20.4); and finally two invited reliability presentations, by Jim Stathis of IBM (20.6) and Tony Oates of TSMC (20.7), on what the challenges are in their field as we move beyond 14/16 nm.

Session 21 is a group of five papers discussing Atomistic Modeling of Device Interfaces and Materials, the first being a multi-national study of hole traps in p-MOSFETs (21.1); I had not realized that such traps had similar characteristics in different oxide dielectrics, whether it be silicon or high-k; and it appears that hydroxyl (-OH) groups could be the cause.

The next three talks (21.2, 21.3, 21.4) are also dielectric and interface studies, as is the last, but 21.5 is focused on HfO and HfAlO-based RRAM.

We go back to MEMS in session 22, actually NEMS as well, as in 22.1, which is a review of integrating NEMS with CMOS (U Grenoble Alpes, CEA-Leti, MINATEC), and 22.4, another CEA-Leti talk on polySi nanowire sensors. Tsing-hua U has two papers also, 22.2 on a nanomechanical thermal-piezoresistive oscillator, and 22.3 on CMOS-MEMS Oscillators. The final two presentations are from A*STAR, about integrating RF MEMS resonators and phononic crystals (22.5), and a 9 degree of freedom capacitive sensor.

That brings us to the end of the afternoon, and Applied Materials is hosting a panel on “The Transistor Revolution” in the Nikko Ballroom in the Nikko Hotel. In parallel Coventor is hosting an event “Survivor, Variation in the 3D Era” in the Carmel Room, also at the Nikko Hotel. They both usually cater us well, so once we’re sated from the hospitality we can wander back to the Hilton for the conference evening panel:

“60 Years of IEDM and Counting: Did we push silicon based devices for integrated electronics to the ultimate and what does the future hold?”

Usually there are two panels, having one avoids conflicts this year; and there are some distinguished panelists – Krishna Saraswat from Stanford University, with two colleagues, Yoshio Nishi and Philip Wong, Chenming Hu (UCal Berkeley), Hiroshi Iwai Tokyo Institute of Technology), Jesus del Alamo (MIT), and Kurt Petersen, co-founder of six MEMS companies, and a member of the Band of Angels.

Wednesday

Wednesday morning has sessions 25 – 31; S25 on III-V for Logic; MIT has two papers, on InGaAs Quantum-Well MOSFETs (25.1), and InGaAs/InAs heterojunction single nanowire vertical tunnel FETs (25.5).

25.2 is an invited review of “High-Performance III-V Devices for Future Logic Applications”, by Dae-Hyun Kim of GLOBALFOUNDRIES; 25.3, by IBM, is more high-performance self-aligned InGaAs-channel MOSFETs; 25.4 (UCal, Santa Barbera) is also InGaAs, but with InP Recessed Source/Drain Spacers; and 25.6 discusses an InAlN/AlN/GaN triple T-shape fin-HEMT (Nanyang TU, Ohio State U, Institute of Materials Research and Engineering).

S26 covers Thin Film Transistors for Display and Large Area Electronic Applications. Imec demonstrates an ultra-low power organic 8 bit transponder chip in 26.1, followed by IBM with heterojunction field-effect thin-film transistors (TFTs) with crystalline Si channels, and gate regions comprised of hydrogenated amorphous silicon or organic materials (26.2).

CBRITE is next up (26.3), on High Performance Metal Oxide TFTs, then a change of pace to carbon nanotubes with sputtered and spray-coated.

26.5 Fig 3 lSi on paper large_Trifunovic

 

Metal oxides to form complementary inverters, from the Swiss Federal Institute of Technology, Imperial College London, and U Würzburg (26.4).

Believe it or not, Delft U has worked out a way to put silicon TFTs on paper or other soft substrates:

“The Delft team made the devices by casting a quantity of liquid polysilane onto a substrate, and forming a thin film from it by “doctor-blading,” or skimming it with a blade. High-performance polysilicon channel regions then were formed by laser annealing, using short pulses of coherent light to selectively crystallize the disordered film. The maximum temperature required was only 150ºC, making the TFTs suitable for paper and plastic substrates such as PET and PEN.” (26.5)

Tsing Hua U finishes up the session with the last two papers – a study of “Ultra-Thin Body (2.4nm) Poly-Si Junctionless Thin Film Transistors with a Trench Structure”, claimed to be useful for displays and 3DICs; and more poly-Si channel junctionless  FETs, but this time with a poly fin (26.6, 26.7).

Hybrid and 3D Integration is the topic of Session 27; TSMC starts off with a review paper about wafer-level system integration technologies (27.1), followed by Nikon, demonstrating their precision-aligning Cu-Cu bonding system for 3DICs (27.2); then TSMC adds high-k metal-insulator-metal capacitors to their CoWoS interposers (27.3).

Stanford U pushes the boundaries in paper 27.4 by integrating traditional silicon-FETs with RRAM and carbon nanotube-FETs, to form four vertically-stacked circuit layers (logic layer followed by two memory layers followed by a logic layer).

27.6 Fig1_Choi

 

CEA-Leti has been working on monolithic 3D integration for a while, and here they consider the thermal budget of the bottom layers (27.5). The last paper has KAIST transferring SOI silicon nanowire SONOS memory onto a plastic substrate, after thinning down to the buried oxide (27.6).

We have more emerging memory papers in session 28, together with a couple on heterogeneous integration. Toshiba starts the session discussing high density STT-MRAM for cache memory (28.1), using MTJs embedded in the back-end stack. Tohoku U and NEC look at hybrid MTJ/CMOS logic in 28.2 to make ultra-low-power logic LSI, and Rambus investigates surge current control in RRAM arrays in 28.3.

Paper 28.4 is a CEA-Leti (et al.) study of pattern recognition using convolutional neural networks made from HfO2 based OxRAM devices as binary synapses. National Chiao Tung U is also researching synaptic use of RRAM for neuromorphic computation in 28.5.

Tohoku U returns with a 3-D stacked multicore processor module made from a 4-layer 3-D stacked multicore processor chip and a 2-layer 3-D stacked cache memory chip (28.6), and using backside TSVs to enable multichip-on-wafer 3D integration. Below is an X-ray tomograph of the TSV stacks, the processor on the left and the memory on the right:

28.6 Figure17_LKW_Tohoku

In 28.7, Penn State U et al. demonstrate coupled hybrid vanadium dioxide FET oscillators in a platform for associative computing, claiming ~20x power reduction compared with CMOS; and the last paper from UCal Berkeley (28.8) integrates NEMS into a CMOS back-end stack for ultra-low power applications.

Session 29 continues the memory theme, discussing PCM and Neural Networks, and kicked off (29.1) by Micron Italy (et al.) looking into different GeSbTe PCM cell architectures.

29.2 Fig1

 

29.2 is from the Japanese LEAP consortium, describing a new type of PCM, “topological-switching random-access memory,” (TRAM). It differs from conventional PCM in that the latter works by the rapid heating of a chalcogenide material, which shifts it between its crystalline and amorphous states; whereas TRAM stores data by movement of germanium atoms within a GeTe/SbTe crystal superlattice:

The authors claim up to 20x reduction in programming energy, achieving a set/reset current as low as 55 µA.

We have an invited paper in 29.3, “Phase Change Memory and its Intended Applications”, by Chung Lam of IBM, followed by a statistical study of PCM to optimize memory capacity (29.4, UCal Berkeley et al.). We get back to PCM-based neural networks in 29.5, again from IBM, and Politecnico di Milano/Micron look at PCM set-transition energies (square vs triangular pulse) in 29.6.

IBM again takes the podium in 29.7, examining access devices for crossbar resistive memories, and they are a co-author with Macronix and National Tsing Hua U in the last paper, detailing a PCM recovery method – apparently a local anneal can be done on-chip to recover the phase-change properties if they degrade due to too many cycles (29.8).

Simulation of Novel Materials and Devices for FETs are considered in session 30; Toyota Tech Institute, Osaka U, and U Tsukuba (30.1) show that random dopant fluctuation in the source region causes a noticeable variability in the on-current of Si nanowire transistors, and its impact is found to be much larger than that of random telegraph noise (RTN).

30.2 is a review of Tunnel-FETs for future low-power technology nodes, by imec; 30.3 (U Florida) simulates Mo-disulphide-WTelluride vertical tunneling transistors; 30.4 (ETH Zurich) is another Mo-disulphide transistor study, as is 30.5, but also evaluates W-diselenide (UCal Santa Barbara); and the session finishes with a simulation of a (B-N) co-doped graphene TFET by Hong Kong UST/NanoAcademic Technologies (30.6).

The last focus session is session 31, Sensors, MEMS, and BioMEMS. It opens with a display of bio-MEMS for handling single molecules, including silicon nano tweezers, arrays of micro chambers, and chips with linear bio molecular motors (31.1, U Tokyo). The specific application is the use of MEMS technology on the molecular scale to conduct studies of DNA degradation and protein mutation related to Alzheimer’s disease. MEMS tweezers were used to trap bundles of DNA molecules to study them for stiffness and viscosity, which are markers of DNA degradation.  Here we have an electron microscope image of a DNA molecular bundle between the tips:

31.1 fig2_Fujita

 

Next up, U Bologna/U Southampton research the use of AC nanowire sensing that can capture both magnitude and phase information of the device response (31.2); 31.3 is a review of “MEMS for Cell Mechanobiology” (Stanford U); and 31.4 is also a review, of “Organic Electrochemical Transistors for BioMEMS Applications”, from Ecole Nationale Supérieure des Mines.

U Cincinnati (et al.) follows, with a tempting look at a “novel multimodality lab-on-a-tube smart catheter”, which can accurately track multiple parameters in an injured brain (31.5); 31.6 (Ritsumeikan U) shows off another medical device, an all polymer pneumatic balloon actuator, fabricated from polymers such as polyimide and polydimethylsiloxane that we are familiar with in the chip business. Paper 31.7 from MC10 completes the session by demonstrating examples of skin-based systems that incorporate physiological sensors and actuators configured in stretchable formats.

After the morning sessions, the IEDM Entrepreneurs Lunch is back for a third year, featuring a presentation by Kathryn Kranen, Former President and CEO of Jasper Design Automation.

Also at lunchtime ASM is hosting their regular IEDM seminar (Wednesday this year, instead of the Monday as of last year) on “14nm & Beyond – Fins all Around”, at the Nikko Hotel across the street from the Hilton. There’s no website, so interested parties should contact Rosanne de Vries, by replying to rosanne.de.vries@asm.com. And there’s a bit of self-promotion here, since I’m one of the guest speakers!

32.1 FIG6-HR_Tsai

 

We are back to Process and Manufacturing Technology in S32 after lunch, with a focus on Advanced Process Modules. IBM details some of its work on finFETs formed by Directed Self Assembly (DSA) in 32.1, achieving 29 nm fin pitch, and maybe giving us more evidence that EUV may never happen..

In 32.2 Samsung discusses their 10-nm interconnect strategy; judging by the abstract, we might be moving to Cu+Ru liner by the time we get to 10 nm. An imec/Micron/Hynix joint paper (32.3) reveals a new front-end scheme (gate and diffusion replacement), which allows high-thermal budget processes for applications such as control logic for memory (e.g. DRAM periphery).

Paper 32.4 is from Albany CNSE and its sponsors, examining the contact resistivity on n+ InGaAs fin sidewall surfaces; U Tokyo discusses oxygen effects in Ge MOSFETs in 32.5; 32.6 is a review of ion implantation techniques and capabilities by Applied Materials, from doping to materials engineering; and 32.7 covers “A Novel Junctionless FinFET Structure with Sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing”. The lead authors are from National Nano Device Laboratories, National Chiao Tung U, and National Cheng Kung U, but Michael Current and Evans Analytical are also involved, so at the least there should be some interesting analytical data included.

Session 33 has Exploratory Devices as the subject, inevitably academic in nature – Carnegie Mellon starts off (33.1) showing a four-terminal spintronic device, followed by Tohoku U, investigating 1x-nm perpendicular-anisotropy CoFeB-MgO based MTJs (33.2). Then we have a two-sided graphene oxide doped silicon oxide based RRAM (33.3) from National Sun Yat-Sen U, Peking U, and Stanford U; and a new material raises its head in (33.4) – iodostannane, basically tin activated with iodine, in a new kind of transistor, the topological-insulator field-effect transistor.

National Nano Device Laboratories, et al., present CMOS-compatible Mo-disulphide 3DFETs in 33.5, and Stanford U end the session with a review of carbon nanotube transistors.

Reliability: BTI, HCI and Breakdown are dealt with in session 34. A SMIC-sponsored work on NBTI in HKMG is covered in 34.1, co-authored by Peking U, Liverpool John Moores U, and UCal Berkeley. Liverpool John Moores U and imec look at NBTI of Ge pMOSFETs (34.2), and AIST has researched PBTI in n-fin-TFETs in 34.3; imec is back in 34.4, reviewing BTI reliability in “beyond-silicon devices”; and 34.5 covers RTN in both SiON and HKMG devices, by Peking U and SMIC.

Samsung (34.6) studies hot carrier induced dynamic variation in nano-scaled SiON/Poly, HK/MG and finFET devices, and the final paper of the session is from IBM and SRDC, discussing breakdown mechanisms in dielectric BEOL stacks (34.7).

The last session (numerically), session 35, covers Compact Modeling of devices. MIT and Purdue U get together to present a new model for FETs, which uses only a few physical parameters and is consistent with the virtual source model (35.1). They demonstrate its accuracy by comparison with measured data for III-V HEMTs and ETSOI Si MOSFETs.

NXP/UFRGS have a new noise (RTN/LFN) model for MOSFETS in 35.2, followed by IBM discussing several width dependent transistor current characteristics (35.3). We jump to TSVs in 35.4, with a CEA-Leti (et al.) study of thermal dissipation in 3D ICs and an associated model; IMECAS presents a surface potential-based compact model for a-IGZO TFTs in RFID applications in 35.5; and Purdue U/GLOBALFOUNDRIES model MTJs in 35.6.

Chronologically the last papers are due at 4.05 pm – by then a lot of attendees will have headed for home, especially since this year’s conference is so close to the Christmas break.

I will definitely be suffering from information overload and becoming brain-numb, but with 218 papers and an average of six parallel sessions at any one time, plus the offsite events, that’s not really surprising. On the other hand, where else do we go to get all this amazing stuff?

Time to unwind, maybe do a little holiday shopping, and go for an indulgent meal.

References:

[1]     H.J. Yoo et al., “Demonstration of a reliable high-performance and yielding Air gap interconnect process”, IITC 2010, pp. 1-3

[2]     J. Jang, et al., “Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High density NAND Flash Memory” VLSI 2009, pp.192-193

[3]     M. G. Farooq et al., “3D Copper TSV Integration, Testing and Reliability”, IEDM 2011, pp.143-146

 

Intel’s 14nm Parts are Finally Here!

By Dick James, Chipworks

Earlier last week, a couple of laptops arrived from Japan using the Core M version of Intel’s Broadwell processor. Straight into the lab, and within a few hours the first sight of the die structure, confirming that it is indeed the 14nm technology.

The first image below is an image of a die that was given a bevel polish, so that we can look at the transistors in plan view. It’s a bit fuzzy, due to the high magnification, and construction we have going on next door; but we have measured ten contacted gate pitches as you can see, and that looks pretty close to the 70nm that was announced by Intel back in August.

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Intel Aug 11_14 slide 16

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On another part of the bevel we can see the fins, and here we have counted 20 pitches (third image above). Which agrees with the 42nm pitch in the Intel webcast. So far, so good!

If we look at the cross-section (fourth image), Intel has stayed with their thick top metal that they have been using since the 65-nm node, which means that we have to squint awfully hard to see THIRTEEN layers of metal, and a MIM-cap layer under the top metal.

10_General_Structure_168232-c-a_branded

A look at the edge seal (fifth image), which doesn’t have the top metal or the MIM-cap, makes it easier to count twelve layers. We are used to seeing twelve-plus metal layers in IBM chips (their 22nm Power8 has fifteen!), but Intel has been using nine for the last few generations, going up to eleven in the Baytrail SoC chip.

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Intel quoted 52 nm interconnect pitch, but we see 54nm (sixth image). Although that is within measurement error, and we may not have sectioned the most tightly packed part of the die.

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As yet we don’t have any detailed TEM imaging to look at the transistors or fins in close-up, so we can’t verify if the fins have vertical walls or not, as shown by Intel (seventh image).

Intel Aug 11_14 slide 22

The cross-section seems to show that essentially the 14nm process is a shrink of the 22nm technology, with the modified fins; the gate metallisation looks similar to the 22nm, with tungsten gate fill as in the earlier process. (As an aside, this will make it the fourth generation replacement metal gate process – this technology has legs!)

Intel and IBM are giving late news papers at IEDM in December, and apparently there are air gaps in the back-end dielectric stack – we have not found those yet. We have confirmed the SRAM cell size in the cache memory is ~0.058 µm2.

Our analysis is ongoing, and we look forward to some great images!

The Second Shoe Drops – Now We Have the Samsung V-NAND Flash

By Dick James, Senior Technology Analyst, Chipworks

Two weeks ago, we posted about the TSMC 20nm product that we had in-house; now after waiting for a year since Samsung’s announcement of V-NAND production, we have that in the lab and can start to see what it looks like.

The vertical flash was first released in an enterprise solid-state drive (SSD) last year, in 960 GB and 480 GB versions, but with no model number, so essentially for sampling only to established customers. Then in May this year they announced a second-generation V-NAND SSD, with a stack of 32 cell layers.

However, on July 1 at this year’s Samsung SSD Global Summit they unveiled the SSD 850 Pro, aimed at high-end PCs and workstations, and said to be available in July. Of course we immediately put out feelers and got some on pre-order.  They showed up last week and we have the first few images.

First, though, let’s think about what the changes are from the conventional planar NAND. Samsung posted a slick video which gives a summary of the technology. The first thing to note is that we have gone from the ETOX floating-gate charge storage that we have seen in the last umpteen generations of flash, to charge-trap storage (CTF – Charge Trap Flash) in which the charge is stored on a silicon nitride layer (otherwise known as a SONOS cell – Si/SiO/SiN/SiO/Si).

The SONOS stack is then oriented vertically, using a polysilicon cylinder as the substrate silicon, and wrapping the other layers around the central cylinder.

Fig. 1  Cell structure transition from planar to V-NAND stack

Fig. 1 Cell structure transition from planar to V-NAND stack

 

The wordlines (control gates) become a horizontal layer, and the bitlines are connected to the top of the polySi cylinder; the select gates are formed by the top and bottom conductive layers [1]. Samsung describes the use of a tungsten replacement metal gate [1], and 24 wordline layers plus 2 dummy wordlines and two select gates for a total of 28 layers [2].

Fig. 2  Schematic of  V-NAND cell stack

Fig. 2 Schematic of V-NAND cell stack

 

We also see in Fig.2 a “blocking layer” in between the metal gate and the SiN, which at least implies the use of a high-k dielectric instead of an oxide layer for the capacitative coupling layer, as used in their CTF parts from 2006.

One of the many challenges using a vertical stack such as the V-NAND is etching through a stack of many dissimilar layers, to etch the holes for the polySi cylinder channels,  the slots through the stack to separate the wordlines, and the vias down to the wordlines (etching holes down to a staircase of extended wordlines). In fact, the whole stack is a big etching problem – see Fig.3.

Fig. 3  Schematic of etching steps in V-NAND stack

Fig. 3 Schematic of etching steps in V-NAND stack

 

Now that we have the production part, Samsung have clearly solved those problems. Let’s take a first look at what’s inside. Fig. 4 is a photo of the die, and Fig. 5 shows the die mark – the “A” on the end denoting the second-generation product. Interestingly, the “DG” in the part number normally denotes a 128-Gb die, but this part is actually ~86 Gb, since we have twelve flash dies in our 128-GB solid-state drive.

Fig.4 Die photo of  Samsung K9ADGD8S0A V-NAND flash device

Fig.4 Die photo of Samsung K9ADGD8S0A V-NAND flash device

The part described in the ISSCC paper [2] was an actual 128-Gb device, with a chip size of ~133 sq. mm. Our 86-Gb die has shrunk to ~85 sq.mm., slightly increasing the bit density from 0.96 to 0.99 Gb/sq.mm.

 

Fig. 5  Die mark

Fig. 5 Die mark

When we cross-section the chip, the staircase shown in Fig. 3 shows up nicely:

Fig. 6  SEM cross-section of Samsung V-NAND stack

Fig. 6 SEM cross-section of Samsung V-NAND stack

In this first shot, we don’t appear to have sectioned through any of the vias to the wordline layers; the vertical features appear to be polySi cylinders drilled into the outer edges of the stack. If we look closer at the edge of the array, that does appear to be the case (Fig. 7).

Fig. 7  Edge of V-NAND flash array

Fig. 7 Edge of V-NAND flash array

On the left side of the image we can see the array proper. SEM images can always be confusing, but it appears that the polySi bitline cylinders are staggered, and the slots between wordlines are filled with tungsten to contact the substrate for the lower select transistors. Fig. 8 shows things in a little more detail, and we can clearly see that the bitline contacts are staggered. We can also see that there are 38 layers in the stack; 32 wordlines, plus four dummy wordlines, plus the select transistors at top and bottom.

Fig. 8  Close-up image of V-NAND flash array

Fig. 8 Close-up image of V-NAND flash array

At the moment, that’s as far as we’ve got; we don’t yet have any materials analysis, but my guess is that the three interconnect layers are tungsten, copper and aluminum, as in a lot of other Samsung memory chips.

We will of course being preparing a report on this seminal part, so for more details contact Chipworks, or keep an eye on my Twitter account, @ChipworksDick.  Once the dust has settled, I hope to get into a bit more detail in a future blog in a few months time.

[1] J. Jang et al., “Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory“, Dig. Symp. VLSI Tech., pp. 192-193, June 2009

[2] K-T Park et al., “Three-Dimensional 128Gb MLC Vertical NAND Flash-Memory with 24-WL Stacked Layers and 50MB/sHigh-Speed Programming“, Proc. ISSCC, pp. 334-335, Feb. 2014

TSMC 20nm Arrives – The First Shoe Drops

By Dick James, Senior Technology Analyst, Chipworks

For us at Chipworks interested in leading edge processes, 2014 so far has been the year of waiting for parts and processes that have been announced, but not shown up in the world of commercial production. It will surprise no-one in the business that they are Intel’s 14-nm, the 20-nm products from any of the big three foundries (in particular TSMC), and vertical NAND (in particular Samsung, since they are the first claiming shipment).

There are of course other products that we are anticipating such as the latest SDRAM, STT or resistive RAM, and anything with TSVs, but they are lower-key and will not get the same attention from the majority of our customers.

So now the first shoe has dropped (must check where that metaphor came from!), and we have a TSMC-fabbed 20-nm part in-house. It is in the lab at the moment, and we are waiting for the analysis results.

It will be interesting to see what changes TSMC has made from the 28-nm process; in general, I expect mostly a shrink of the latter process, with no change to the materials of the high-k stack, though maybe to the sequence. At 28-nm the high- k was put down first, before the dummy poly gate, and it makes sense to move that deposition to after poly gate removal. That way, the high-k layer does not have to suffer the poly formation and source-drain engineering process steps, saving it from quite a bit of thermal processing.

Below is an illustration of a NMOS transistor from a Qualcomm Snapdragon 800, fabricated in the TSMC 28HPM process. The slight indent at the bottom of the metal stack (indicated by the arrow), above the high-k layers, indicates that the high-k was formed before the polysilicon deposition and the subsequent source/drain engineering.

Fig. 1: NMOS Transistor in Qualcomm Snapdragon 800

Fig. 1: NMOS Transistor in Qualcomm Snapdragon 800

The dark line at the perimeter of the metal gate is the tantalum-based barrier layer between the Ti-Al work-function doping layer and the TiAlN work-function layer, and is the first layer formed after the dummy poly removal. Intel used this sequence for their 45-nm process, but modified it at the 32-nm node to deposit the high-k stack after poly removal (high-k last – see below).

Fig. 2 Intel 32-nm NMOS Transistor

Fig. 2 Intel 32-nm NMOS Transistor

You can see that Intel also adopted raised source/drains, with stacking faults to apply tensile stress; we will see if TSMC does the same in their second generation gate-last HKMG process. They could also change the gate fill metal, since in a smaller gate it may be difficult to use the PVD Ti/Al/Cu from the 28nm sequence.

Fig. 3 PMOS Transistor in Qualcomm Snapdragon 800

Fig. 3 PMOS Transistor in Qualcomm Snapdragon 800

When it comes to PMOS, I also expect a high-k last version of the 28-nm gate structure, with the latest version of e-SiGe source/drains, likely with a sigma-cavity etch to the (111) planes. We already have raised source/drains, and the Ge content is ~50%, so not much opportunity for change there.

As for the back-end, presumably there will be a reduction in the k-value of the low-k dielectric, and maybe some thinning of the barrier layer in the metal trenches, both of which are trends that progress relatively slowly by comparison with the front-end.

Back in May, Applied Materials announced a cobalt CVD system aimed at improving copper fill and electro-migration performance. I wouldn’t have expected to see this in use yet, but at Semicon I heard that over 90 of these systems have already been shipped, so there is at least a possibility that we’ll see cobalt in our 20-nm metallization.

All pure speculation, but as a blogger and analyst, I’m paid to speculate!

As for “the first shoe drop”, it’s a variant on “waiting for the other shoe to drop“; apparently it’s a reference to cheap apartment housing where tenants would hear their neighbours above taking off and dropping their first shoes on to the floor; and then wait for the second shoes to drop.

Intel’s e-DRAM Shows Up In The Wild

When Intel launched their Haswell series chips last June, they stated that the high-end systems would have embedded DRAM, as a separate chip in the package; and they gave a paper at the VLSI Technology Symposium [1] that month, and another at IEDM [2].

It took us a while to track down a couple of laptops with the requisite Haswell version, but we did and now we have a few images that show it’s a very different structure from the other e-DRAMs that we’ve seen.

IBM has been using e-DRAM for years, and in all of their products since the 45nm node. They have progressed their trench DRAM technology to the 22nm node [3], though we have yet to see that in production.

Embedded DRAM in IBM Power 7+ (32-nm)

Embedded DRAM in IBM Power 7+ (32-nm) (Click to view full screen)

TSMC and Renesas have also used e-DRAM in the chips they make for the gaming systems, the Microsoft Xbox and the Nintendo Wii. They use a more conventional form of memory stack with polysilicon wine-glass-shaped capacitors. TSMC uses a cell-under-bit stack where the bitline is above the capacitors, and Renesas a cell-over-bit (COB) structure with the bitline below.

Embedded DRAM in Microsoft Xbox GPU fabbed by TSMC (65-nm)

Embedded DRAM in Microsoft Xbox GPU fabbed by TSMC (65-nm) (Click to view full screen)

Intel also uses a COB stack, but they build a MIM capacitor in the metal-dielectric stack using a cavity formed in the lower metal level dielectrics. The part is fabbed in Intel’s 9-metal, 22nm process:

Embedded DRAM in Nintendo Wii U GPU fabbed by Renesas (45nm)

Embedded DRAM in Nintendo Wii U GPU fabbed by Renesas (45nm) (Click to view full screen)

When we zoom in and look at the edge of the capacitor array, we can see that the M2 – M4 stack has been used to form the mould for the capacitors.

General structure of Intel’s 22-nm embedded DRAM part from Haswell package

General structure of Intel’s 22-nm embedded DRAM part from Haswell package (Click to view full screen)

Looking a little closer, we can see the wordline transistors on the tri-gate fin, with passing wordlines at the end of each fin. Two capacitors contact each fin, and the bitline contact is in the centre of the fin.

Intel’s 22-nm embedded DRAM stack

Intel’s 22-nm embedded DRAM stack (Click to view full screen)

We can see some structure in the capacitors, but at the moment we have not done any materials analysis.  A beveled sample lets us view the plan-view:

Plan-view image of the Intel 22-nm embedded DRAM capacitors

Plan-view image of the Intel 22-nm embedded DRAM capacitors (Click to view full screen)

The capacitors are clearly rectangular, but again in the SEM we cannot see any detailed structure. We’ll have to wait for further analysis with the TEM for that!

Intel claims a cell capacitance of more than 13 fF and a cell size of 0.029 sq. microns, so about a third of their 22-nm SRAM cell area of ~0.09 sq. microns, and a little larger than the IBM equivalent of 0.026 sq. microns. The wordline transistors are low-leakage trigate transistors with an enlarged contacted gate pitch of 108 nm (the minimum CGP is 90 nm).

In the Haswell usage the die is used as a 128 MB L4 cache, with a die size of ~79 sq. mm, co-packaged with the CPU.

Intel Haswell CPU with co-packaged eDRAM

Intel Haswell CPU with co-packaged eDRAM (Click to view full screen)

Intel got out of the commodity DRAM business almost thirty years ago; it will be interesting to see where they take their new entry, though not likely into competition with the big three suppliers. Their “Knights Landing” high-performance computing (HPC) platform is reported to use 16 GB of eDRAM, which will take the equivalent of 128 of these chips, so perhaps the future is in HPC and gaming systems such as the one we bought to get the part.

References

[1] R. Brain et al., A 22nm High Performance Embedded DRAM SoC Technology Featuring Tri-gate Transistors and MIMCAP COB, Proc VLSI Symp 2013, pp. 16-17.

[2] Y. Wang et al., Retention Time Optimization for eDRAM in 22nm Tri-Gate CMOS Technology, Proc IEDM 2013, pp. 240-243.

[3] S. Narasimha et al., 22nm High-Performance SOI Technology Featuring Dual-Embedded Stressors, Epi-Plate High-K Deep-Trench Embedded DRAM and Self-Aligned Via 15LM BEOL, Proc. IEDM 2012 pp. 52-55.