Chipworks



GLOBALFOUNDRIES Takes a Different Approach to HKMG in AMD’s Llano CPU/GPU

After much anticipation, and with quite a few design wins, AMD’s Llano CPU/GPU chip arrived on the scene a couple of months ago. Fabricated by GlobalFoundries (more easily known as GloFo) in their 32nm SHP process, it was the first foundry-based gate-first HKMG product to come on the market.

As a processor, it garnered pretty favorable reviews, but of course we were keen to get it into the lab and see how it had been put together. When we did, it became a bit of a mystery — we couldn’t see any significant differences in gate stack between NMOS and PMOS! It’s common wisdom that you need different work function materials in the NMOS and PMOS gates to differentiate them and make up the CMOS circuitry.

For example, Panasonic uses lanthanum to tweak the work function of their NMOS transistor and distinguish it from the PMOS stack in their HKMG Uniphier chip that we looked at back in the spring.

Fig. 1  Panasonic 32-nm HKMG Transistor

As we can see in Fig. 1 above, the gate metal is titanium nitride under the polysilicon, and the hafnium-based high-k layer is below that, over the interface oxide. There was no apparent physical difference between NMOS and PMOS until we start looking in detail, and then we found just a tickle of lanthanum in the NMOS stack, but presumably enough to move the work function into the NMOS regime.

When we look at the Llano, it also uses a gate-first transistor style, with TiN as the gate metal, but there the resemblance stops. Below (Fig. 2) is a composite image of the Llano NMOS/PMOS transistors, and you can see that they are more complex.

Fig. 2  AMD/GloFo 32-nm HKMG NMOS and PMOS Transistors

Dual-stress liners are used to add tensile and compressive stress; we can see from the above that the PMOS (compressive) nitride is twice as thick as the NMOS (tensile) layer. The PMOS device also has embedded SiGe in the source/drains to add more compressive stress, whilst there is possible evidence of stress memorization (SMT) for NMOS. And if we look carefully, the PMOS SOI layer is also a little thicker than the NMOS SOI.

The NMOS and PMOS gate stacks shown in Fig. 3 appear to be the same — highly silicided poly on a thin AlO barrier layer, on TiN gate metal, which is on the Hf-based hi-k layer with a SiO interfacial layer on the substrate. The AlO layer in the PMOS stack is more diffuse, and some of the aluminum has migrated into the TiN, and arsenic is present as expected in the NMOS, but essentially they are the same.

Fig. 3  AMD/GloFo Transistor Gate Stacks

So now we have a bit of a mystery; how are the NMOS and PMOS transistors differentiated? We looked long and hard in both NMOS and PMOS for a dopant such as the lanthanum used by Panasonic, something other than hafnium, silicon, or titanium, but if it’s there’s, it’s below the detection limits. Aluminum is known as a dopant for PMOS, but to be effective it has to be present at the Hf/SiO interface to create Vt-shifting electrical dipoles, and we see no evidence of migration that far.

The extra thickness in the SOI is the clue to what we think is going on in this part. The extra thickness is actually a layer of epitaxial SiGe, which changes the relationship with the gate metal and shifts the Vt, instead of using a dopant in the hi-k. Some work was done on this topic at SEMATECH a few years ago [1], and of course AMD and IBM were members and would have received the results.

The schematic in Fig 4 shows conceptually what happens; the valence band of the substrate is shifted because of the Ge, and also due to the compressive strain applied by the embedded SiGe source/drain and the nitride stress layer.

Fig. 4  Schematic of Band Diagram for Transistor with SiGe Channel [1]

Fig. 5 illustrates the drive current improvement for a >10% SiGe channel in the SEMATECH device, which will also include the effect of the inherent improved hole mobility in the SiGe.

Fig. 5  Drive Current Improvement in SiGe-Channel Device

That accounts for the PMOS; the NMOS was still a bit of a mystery, since one would still expect a dopant at the hi-k/oxide interface, and we see none. All we see is TiN, and Intel uses that as their PMOS work-function metal, which which on the face of it  doesn’t make sense. However, more SEMATECH [2, 3] work indicates that the work function of TiN can be manipulated by adjusting the growth conditions and thickness, enough to shift it from the NMOS to the PMOS regime.

In fact, SEMATECH’s ESSDERC paper from 2005 [3] agrees nicely with what we see in the AMD and Intel parts. The Llano has a ~2nm TiN layer in the NMOS, whereas Intel uses ~2nm layer plus a 1nm Ta-based cap and another ~4nm TiN on top of that in their PMOS. Fig. 6 indicates that this extra material could be enough to move the work function in Intel’s transistor from NMOS to PMOS.

Fig. 6   Effective Work Function of TiN electrode when 10-nm thick ALD TiN and TaN Films are Used as Overlayers on ~3.6 nm TiN Layer [3]

We actually had a clue a couple of years ago, if we had known what we are looking at. In a CICC paper [4] GlobalFoundries showed an image (Fig. 7) of a transistor that looks as though it had a SiGe channel — but of course they didn’t say so!

Fig. 7  Experimental  GLOBALFOUNDRIES Transistors [4]

Of course all of the above is pure speculation, but if the literature is correct it, does hang together and account for the difference between this latest HKMG product and the others we have seen. Now, will IBM, Samsung, and the other alliance members do the same thing?

References

1. H.R. Harris et al., Band-Engineered Low PMOS VT with High-K-Metal Gates Featured in a Dual Channel CMOS Integration Scheme, Symp. VLSI Technology 2007, pp 154-155

2. K Choi et al., Growth Mechanism of ALD-TiN and the Thickness Dependence of Work Function, Symp. VLSI Technology 2005, pp 103-104

3. K. Choi et al., The Effect of Metal Thickness, Overlayer and High-k Surface Treatment on the Effective Work Function of Metal Electrode, ESSDERC 2005, pp 101-104

4. S. Krishnan et al., Advanced SOI CMOS Transistor Technologies for High-Performance Microprocessor Applications, CICC 2009

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