By Dick James, Senior Technology Analyst, Chipworks
The Confab started on Tuesday last week, an industry get-together organised by Solid State Technology (part of Extension Media), which they promote it as the “Semiconductor Manufacturing & Design Industry’s Premier Conference and Networking Event”.
The conference portion started with an afternoon panel session, “Exploring the Edges of Semiconductor Technology and Business”; I had the pleasure of kicking it off with a presentation on the state of the art in the business, as seen by Chipworks, then we got together on the podium for the panel part of the discussion.
Pete Singer moderated, and the other panelists were my co-blogger Phil Garrou, and Gopal Rao, ex-Intel and now an independent consultant. Pete had a set of pre-prepared questions on where we thought the business was going, the progress of 3DIC, and what we thought the impact of IoT (internet of things) might be.
We did our best to answer these and other questions from the floor, but Phil brought up a point that resonated with me; in the major segments of our industry we’re now down to three players, and that’s a sign that those segments have probably consolidated as much as they can. In the same way the auto industry has consisted of three significant players in each continental market (three in North America, three in Europe, etc). It’s a bit of an arm-wavy argument, but I think that it’s at least arguable.
So in DRAM we have Samsung, Micron, and SK-Hynix; in flash we have Samsung, Micron, SK-Hynix, and Toshiba/Sandisk: and in leading-edge logic we have Samsung+GLOBALFOUNDRIES, Intel, and TSMC.
Subramani Kengeri from GLOBALFOUNDRIES gave a good illustration of this a couple of years ago in an ASMC keynote speech:
And Tom Caulfield (also GLOBALFOUNDRIES) followed it up at this year’s ASMC, specifically in the DRAM space:
This is a point also made by Bill McClean of ICInsights in recent years, but he continues the logic to argue that now we are a mature industry, the business will tend to follow the world economic cycle rather than the capacity-based boom/bust cycles that we have seen in the first few decades.
Which makes sense from the mile-high perspective – we have all seen the changes in the customer base from the defence and computer industries, through the PC era, to a largely consumer-driven set of products – Apple is now the largest buyer of silicon chips in the world, after all.
Bill bracketed the Confab sessions neatly by giving the final presentation – “Are IC industry cycles dead or just sleeping?” His conclusion was that they are likely sleeping, but the trigger has changed from chip-making overcapacity or shortage, to whether world GDP goes positive or negative. To support that contention, he showed the correlation between worldwide GDP and IC market growth is now better than 0.9, compared with 0.35 back in the eighties.
This trend is likely a result of the consolidation of companies that we’ve seen and will continue to see, combined with the move to fabless and fab-lite, and its consequent tighter control over Capex; and, last but not least, the lack of disruptive new entrants to build mega-fabs and add over-capacity. China has had its play, India does not seem to want to get into that end of the business, and the Russian economy doesn’t seem to be up to it.
So, while we will see periods of growth and recession as always happens, likely amplified for our business since we are now so tied to consumer cycles, hopefully we won’t see the disruptive/destructive ups and downs that old-stagers like me have seen every three – five years in the last four and a half decades.
Having said that, there will be challenges, and it’s hard to see beyond 2020. We are now in the 14nm era in logic processes, and in five years (assuming a two-three year gap between generations) we will be ramping up seven-nm and heading for five.
In DRAM, Samsung has three 1x-nm nodes in their roadmap, possibly spread over five years, and flash is already at 14 – 16nm and moving to vertical – but how long will that last? Theoretically, I guess v-NAND could shrink from its current ~40nm node down to ~15nm, with more layers stacked together.
(That gives us the prospect of multi-Terabits on a single die, and I guess server farms would likely love such a product. On the consumer side, it does make me wonder if there is actually a market for (say) a 16-TB MicroSD card. On the whole, it starts to make my brain hurt.)
Those thoughts left me leaving the Confab actually wondering where these mainstream products are going to be in the early twenties, or if the technology is going to run out of steam. I know we’ve had these thoughts before, mostly due to mis-perceived lithography limits, but now we’re getting to the point where there may not be enough atoms or electrons to do what we want to do using current techniques.
Of course the research consortia are busy looking at ways of getting past this apparent impasse, it’s just that there seem to be quite a few options and no clear winner at the moment. And all the above doesn’t even consider the possible introduction of EUV and/or 450mm wafers.
Time will tell, and I may be retired by then, but we do live in interesting times, and it’s not going to change..