By Dick James
I’ve been looking back at the talk given by Mark Bohr and Zane Ball (Building Winning Products with Intel® Advanced Technologies and Custom Foundry Platforms) at the Intel Developer Forum (IDF) in August last year, and I’m a bit puzzled.
Mark announced the gate pitch as 54 nm, which I make as 0.77 x 70 nm (the 14-nm gate pitch):
And he also said that their measure of scaling is gate pitch x cell height:
and then he said that new design rules give even better scaling:
“Our trend in reducing logic cell area has been about 0.46x per generation, a little bit faster than the typical Moore’s Law of 0.5x.
On our last two generations, 14 nm and now on 10 nm, we’re actually scaling our logic cell area a little bit faster than what that simple metric suggests; there are some other tricks that we’re doing on 10 nm that is providing even faster than normal logic cell area scaling, so although 0.46x was the long-term trend over the past four generations, it’s actually a bit faster on our 14 and now again on our 10-nm technology.”
If you look at the numbers in the revised graph, then we appear to have a scaling factor of ~0.37 per generation, which is indeed quite impressive!
The cell height can also be measured by the number of metal tracks that are needed for routing for the cell; in recent nodes we have gone from 12-track (12T), to 9T, to ~7.5T in the latest 14- and 16-nm processes. So we can also describe cell height as the number of metal pitches (MPP) in a cell.
That leads me to the enigma – if you take the 10-nm number from the above graph, ~11,000 nm2, and divide the 54-nm gate pitch into it to get the cell height, and then divide that by the minimum SADP (self-aligned double patterning) metal pitch of ~40 nm to get the number of tracks, then you get a five-track cell, which seems really ambitious for a one-generation shrink.
If you go the other way and plug in 54 nm and a six-track cell, then the MPP comes out at 34 nm, which presumably means SAQP (self-aligned quadruple patterning), which again sounds really ambitious.
The 5T cell is more in keeping with “design rule enhancements” but if that is the case, that also requires a reduction in the number of fins per transistor, which implies taller fins or other tweaks to maintain transistor performance; or SAQP for fin definition, to allow increased fin density. Given that the 14-nm fin pitch was ~42 nm, already close to the SADP limit, the latter may be a real possibility (a 76% linear shrink would be ~32 nm).
If they’ve done any of these, I guess it could account for the increased time between generations!
Mark also broke with the current convention of showing performance plots with the dreaded “arbitrary units”, later in the talk he showed the four transistor options available in their 10-nm process:
According to Mark, the four options will use the same 54nm gate pitch. NMOS drive currents are still higher than PMOS, which to me suggests two things – there is a seventh-generation strain mechanism at work for NMOS, and it seems unlikely that we have a different channel material such as SiGe in the PMOS devices.
In keeping with their foundry ambitions, there will be three evolutions of the 10-nm process, with the initial launch of 10, then 10+ and 10++, as well as a SoC version of the process with high-voltage and analog elements, and three interconnect stacks. In any case, these numbers do support the Intel claim that their process is a true shrink from 14 nm, not just an improved 14-nm process.
The increased shrink allows Intel to stay ahead of the cost curve, so that we still have improved PPAC (performance/power/area/cost) numbers.
We will see if any more information comes from the quarterly call this week, or at the Investor Meeting next month, but in the meantime, we have our mystery – do we have a five-track cell, or am I missing something?