IEDM 2017 Next Week Part 1

By Dick James

On December 2nd – 6th the good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2017 IEEE International Electron Devices Meeting. To quote the conference website front page, IEDM is “is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.”

That’s a pretty broad range of topics, but from my perspective, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years. Though these days process papers actually tend to be after the launch of the relevant product, such is the preoccupation with trade secrecy.

In the last few weeks I’ve gone through the advance program, and here’s my look at what’s coming up, in more or less chronological order. As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.


Again this year the conference starts on the Saturday afternoon, with a set of six 90-minute tutorials on a range of leading-edge topics:

  • The Evolution of Logic Transistors toward Low Power and High Performance IoT Applications, Dae Won Ha, Samsung Electronics.
    This tutorial will cover the evolution of logic transistors; then, state-of-the-art FinFETs, including layout, key design rules, short channel effects, multi-Vth engineering, local layout effects (LLE), variability, etc. Finally, potential future GAA (Gate-All-Around) device architectures such as MBCFET (Multi-Bridge Channel FET) and VFET (Vertical FET) will be discussed.
  • Hardware Opportunities in Cognitive Computing: Near- and Far-Term, Dr. Geoffrey Burr, Principal Research Staff Member, IBM Research-Almaden.
    This talk reviews recent progress towards brain-inspired computing architectures, ranging from systems that combine CMOS devices in different and unconventional ways, to those built around emerging NVM (Non-Volatile Memory) devices; and from systems designed to accelerate conventional ML (Machine Learning) through hardware innovation, to systems that seek to transcend the limitations of current ML algorithms, e.g. the requirement for batch-based learning using vast datasets of static and labeled data.
  • Silicon Photonics for Next-Generation Optical Interconnects, Dr. Joris Van Campenhout, Program Director Optical I/O, Imec
    First, Joris discusses short-reach optical interconnect scaling trends and the industry roadmap, then the variety of silicon photonics devices; how these building blocks can be combined with low-power CMOS driving circuits to implement Tb/s scale electro-optical transceivers, and finally, the future prospects for integrating GaAs and InP based laser sources on silicon by direct epitaxial growth.
  • Negative Capacitance Transistors, Prof. Sayeef Salahuddin, UC Berkeley.
    Sayeef will review the physical origin of negative capacitance, and how it can be used to amplify the electrostatic field. If combined a transistor gate, this stabilized negative capacitance could lead to supply voltage reduction and/or increase of the ON current. Current understanding of this phenomenon will be reviewed, together with possible pathways to optimize transistor performance for scaled nodes.
  • Fundamental, Thermal, and Energy Limits of PCM and ReRAM, Prof. Eric Pop, Stanford University.
    Dr. Pop will explain the operation and limitations of non-volatile phase-change memory (PCM) and resistive random-access memory (ReRAM), presenting the two memory types in context, and emphasizing their thermal and energy limitations. He will also discuss modern devices, challenges, test structures, and simple models required to understand their operation.
  • 2.5D Interposers and High-Density Fanout Packaging as Enablers for Future Systems Integration, Dr. Venkatesh Sundaram, Associate Director, Georgia Tech 3D Systems Packaging Research Center.
    This talk will introduce interposer and fanout packaging technologies, their market drivers, application examples and infrastructure evolution, and the latest state of the art innovations. Emerging fanout technologies such as TSMC’s InFO used in Apple iPhones, Intel’s embedded bridge (EMIB) technology, and silicon, organic and glass 2.5D interposers will be reviewed.

The first three are from 3.15 – 4.45, and the remainder from 5.00 – 6.30, half an hour later than last year; but a little easier for those of us that fly in on Saturday. This year I hope to make it to the Samsung/IoT session, and possibly the packaging talk at 5.00.

On Sunday December 3rd, we start with the short courses, “Boosting Performance, Ensuring Reliability, Managing Variation in sub-5nm CMOS” and “Memories for the Future: Devices, Technologies, and Architecture”.

Last year the process short course was “Technology Options at the 5-Nanometer Node” so I guess we will see how things have evolved beyond 5 nm.

This year’s effort is organized by Sandy Liao (Intel), and will feature the following sessions:

  • Transistor Performance Elements for 5nm Node and Beyond, Gen Tsutsui, IBM.
    Gen will focus on Si- and SiGe-based FinFET technologies, and discuss transistor optimization in terms of mobility and reliability, and also discuss issues specific to the gate-dielectric interface on SiGe channels. The IBM consortium used SiGe channels in their gate-first PMOS high-k, metal gate (HKMG) devices, so there is solid experience to draw on for this part of the talk.
  • Multi-Vt Engineering and Gate Performance Control for Advanced FinFET Architecture, Steve CH Hung, Applied Materials.
    Steve will focus on gate-stack engineering for advanced FinFETs, in particular from a Vt-modulation perspective using work-function engineered metal-gate electrodes. We are now seeing multiple-Vt options in the leading-edge processes, so this should help us understand how that is done.
  • Sub-5nm Interconnect Trends and Opportunities, Zsolt Tokei, Imec.
    Zsolt is imec’s Distinguished Member of Technical Staff, Interconnect, and gave a talk on “Challenges of 10nm and 7nm Advanced Interconnect” as part of the IEDM 2013 short course, as well as covering “How to Solve the BEOL RC Dilemma?” at the imec Technology Forum at Semicon West this year. He will deal with EUV-related fabrication challenges, track height scaling in standard cells, novel conductor materials, as well as performance issues such as trade-offs in power rails and signal wires and circuit sensitivity to RC delay. Quite a lot to cover in an hour or so! Now we know that Intel is using cobalt interconnect in their 10-nm process, the materials segment will definitely be apposite.
  • Transistor Reliability: Physics, Current Status, and Future Considerations, Stephen M. Ramey, Intel.
    In this session we will hear about transistor reliability issues such as gate oxide integrity, self-heating and transistor aging issues like BTI and hot carrier effects; none of them new, but at 5 nm and below there may be extra complications.
  • Back End Reliability Scaling Challenges, Variation Management, and Performance Boosters for sub-5nm CMOS, Cathryn Christiansen, GLOBALFOUNDRIES.
    Cathryn will start with an overview of reliability basics and improvements established for TDDB and EM through the 7nm node, and then follow-up with a discussion of potential boosters for 5nm nodes and beyond, including asymmetric spacing, thinner barriers/liners, alternative metals, lower-k dielectrics, airgap, and self-aligned vias.
  • Design-Technology Co-Optimization for Beyond 5nm Node, Andy Wei, TechInsights.
    Andy will wrap up the short course with a presentation about design-technology co-optimization (DTCO) for beyond the 5nm node. Andy joined Chipworks (now TechInsights) a couple of years ago, and has ramped up their process and design architecture offerings by an order of magnitude. Those who attended the 2013 short course may remember his session on “Process Integration Challenges in 10nm CMOS Technology”, so he’s a seasoned speaker; and now he’s had the benefit of examining all the 16, 14, and 10-nm offerings since then, so we are likely to get some original commentary.

His topics will be:

  • I thought Moore’s Law was dead: What’s driving accelerated scaling?
  • DTCO Overview: PPA + C + TTM
  • Challenges: beyond the 40-nm pitch barrier and Gate All Around
  • Beyond 5-nm device option evaluation
  • System level innovation and future product requirements

Kevin Zhang from TSMC (formerly Intel) set up the memories short course, apposite now that we are in an era of increasing memory demand, from mobile to server to automotive, not to mention IoT, each with their own challenges.

Intel posted this graphic looking at data storage as equivalent to beer storage, which is a fun way to look at it:

disruptive tech


Of course, that was a plug for their Optane 3D-Xpoint technology, but I guess we can see the automotive use there, and IoT memory in everything from the bottle to the mega-mart…

So we have:

  • Embedded Non Volatile Memory for Automotive Applications”, Alfonso Maurelli, STMicroelectronics.
    Alfonso will review the scaling of embedded nonvolatile memories for automotive applications. He will present the key technology scaling challenges and discuss their solutions to drive eNVM technology to meet the future requirements for automotive electronics.
  • 3D ReRAM: Crosspoint Memory Technologies”, Nirmal Ramaswamy, Micron.
    Nirmal will follow with a technology overview of ReRAM technology for 3D Crosspoint Memories. This new class of memory boasts an unparalleled storage density while rivaling DRAM in terms of access latency. Micron is the other half of the 3D XpointTM partnership – will we get more details of what’s in there?
  • Ferroelectric Memory in CMOS Processes”, Thomas Mikolajick, Namlab. Thomas will discuss the key breakthroughs in ferroelectric devices that have the potential to bring this memory into CMOS-based technologies for embedded applications.
  • Embedded Memories Technology Scaling & STT-MRAM for IoT & Automotive”, Danny P. Shum, GLOBALFOUNDRIES.
    Danny will present state-of-the-art STT-MRAM memories and their applications. Spin-Transfer-Torque (STT) MRAM has drawn lots of interest in recent years due to its unique memory characteristics and scalability.
  • Embedded Memories for Energy Efficient Computing”, Jonathan Chang, TSMC. Jonathan will go through the embedded memory landscape, what is needed for energy efficient computing, SRAM scaling, eFlash for automotive, and MRAM for IoT and mobile applications, and RRAM for IoT.
  • Memory Centric Abundant Data Computing”, Subhasish Mitra, Stanford U.
    Here we will hear about the memory wall in processors and accelerators; in-memory compute, monolithic 3D Integration vs TSV 3D, interwoven memory, logic and sensor arrays using heterogeneous technologies, and abundant data applications such as graph analytics and deep learning,

I would call both courses a full day, seeing as we finish at ~5.30 p.m., but it’s worth sticking around to the end.

If you have the stamina, at 5.30 CEA-leti is holding a Devices Workshop across the street at the Nikko Hotel, and at 6.30 imec is hosting a Technology Forum at the Grand Hyatt San Francisco, on Stockton Street.



Monday morning, we have the plenary session, with three pertinent talks on the challenges and potential of contemporary electronics:


  • Multi-Chip Technologies to Unleash Computing Performance Gains over the Next Decade, Lisa Su, AMD.
    Hot on the heels of their latest batch of successful CPU launches, Lisa will explain how techniques such as system, architectural and software innovation have extended high-performance processor performance. Some of these will continue, but new innovations are needed, especially at the system level, to continue improving performance over the next decade. Multi-chip technologies and system-level innovations will be key.
  • Energy Efficient Computing and Sensing in the Zettabyte Era: from Silicon to the Cloud”, A. M. Ionescu, Nanolab, Ecole Polytechnique Fédérale de Lausanne
    This paper is a look at some of the great research challenges and opportunities for 21st Century energy efficient computing and sensing devices and systems, in the context of the IoT revolution. In future, major innovations in Information and Communication Technologies (ICT) will need holistic approaches including silicon and cloud technologies, centered on big/deep data and context. The monstrous amounts of stored, computed, communicated and sensed information will test the world’s capability of efficiently managing zettabytes of data.
  • System Scaling for Intelligent Ubiquitous Computing”, J. Y-C. (Jack) Sun, Taiwan Semiconductor Manufacturing Company.
    In this talk it looks like Jack is extrapolating what can be done when we really get 3D going:
    “Wafer based 3Dx3D system scaling revolutionizes machine learning (ML) and artificial intelligence (AI) as well as mobile computing. It may trigger a big bang in intelligent ubiquitous computing. 3D CMOS scaling continues with many challenges and opportunities for relentless innovation in materials, processes, devices, circuits, design, EDA, computing architectures, algorithms, and software. 3D stacking and heterogeneous system integration, e.g., CoWoS® and InFO, not only augments but also amplifies the benefits of 3D CMOS logic, 3D memory, integrated specialty technologies and 3D sensors for intelligent ubiquitous computing. The virtuous cycles of 3Dx3D system scaling innovation may expand like a galaxy or universe. The aggregate transistor count in a 3Dx3D sub-system may reach the equivalent of human brain in the 2020s to provide brain-like augmented intelligence.” Whew!


Three quality presentations in three hours, but beware of numb bum if you take in all of them – get up and have a stretch in between, and take a walk before lunch!

After lunch, in keeping with IEDM’s tradition of intellectual overload, we have nine parallel sessions, but this year – now we have exhibitors, we have coffee breaks!

Session 2: Memory Technology – ReRAM and Selectors

Session 2 starts a track on Memory Technology, the first of five. It begins with a paper by SK Hynix (2.1) on selector technology for a cross-point ReRAM; metal atoms were injected into oxide films, and off-current and threshold voltage (Vth) were controlled by using arsenic doping. A one selector-one resistor (1S1R) memory was successfully demonstrated.

SiO2-based ReRAM selector (source; SK Hynix/IEDM)

SiO2-based ReRAM selector (source; SK Hynix/IEDM)

Selectors are again the topic of a collaborative presentation (2.2) from Macronix and IBM TJ Watson Research, this time an Ovonic Threshold Switch (OTS) structure using TeAsGeSi, incorporating Se and an extra dopant (not stated). Excellent endurance is claimed, and robust characteristics after 350 C/30 mins annealing; and the thin film could withstand 500 C annealing. TechInsights has revealed that the selector switch in Intel’s Optane 3D XpointTM products is Se0.44As0.29Ge0.1Si0.17, somewhat similar since Te and Se are in the same group in the elemental periodic table.

Paper 2.3, from an array of French research institutes, studies the programming and reading operations in HfO2-based RRAM cells using OTS selectors, and proposing a new reading strategy. In 2.4, SMIC and collaborators describe a 28-nm, BEOL-based RRAM using one extra mask, though in the abstract they don’t give any details of its structure.

Macronix presents again (2.5) on transition metal oxide (TMO) ReRAMs, studying the retention of the high resistance state, and finding that it is composed of three stages — extending tail-bits, distribution shift, and distribution broadening. Winbond shows a SPI interface, 90-nm 512-Kbit HfO2 RRAM in 2.6; and the last paper in this session is from the Chinese Academy of Sciences (CAS), discussing an 8-layer, 3D Vertical RRAM using a self-selective cell (SSC) with non-filamentary switching. An extreme-scaled structure with 5 nm size and 4 nm vertical pitch was also demonstrated (2.7).

Session 3: Focus Session – Process and Manufacturing Technology – 3D Integration and Packaging

This session consists of invited papers, starting with a paper (3.1) that looks like a review of CEA- leti’s CoolCube monolithic 3D stacking technology. One of the challenges is keeping the thermal budget down so that the first transistor layer is not destroyed by annealing of the higher transistor layers; the authors claim that stacked FETs and ULK/metal lines between stacked tiers can be achieved with a 500°C thermal budget.

Next up, (3.2) Sony displays their 3- layer pixel/DRAM/logic stacked CMOS image sensor first detailed at ISSCC this year. Having the DRAM in the stack allows a camera system capable of 960 fps, launched in the Experia XZ Premium and XZs phones.

In 3.3 we hear about miniaturized and integrated Power Supply on Chip (PwrSoC) and Power Supply in Package (PwrSiP) platforms, from Tyndall National Institute in Eire, enabled by the application of thin-film, integrated magnetics on silicon; a process flow for, and the design of, a thin-film coupled-inductor, switching at 60 MHz, is described.

In paper 3.4, Rao Tummala of Georgia Tech takes a different look at 3D, considering the system package architecture as a way of improving latency and bandwidth between logic and memory, rather than the 3D stacking of ICs with TSVs. In contrast, GLOBALFOUNDRIES (GF) contributes 3.5, how TSVs will enable continued scaling.

TSMC’s InFO (Integrated Fan-Out) technology is the subject of 3.6, seen in the last three iPhone iterations, but not to my knowledge in any other product as yet. In their 2Q17 analyst call, C.C. Wei stated that they had put $1B capex into InFO, and revenue at that point was $500M; and volume production for other customers would not start until 2018.
The session finishes with an IBM-led team describing several novel heat removal and power delivery technologies aimed at making so-called computing cubes a reality (3.7). They tried dual-side cooling of a stack of chips, interlayer cooling, integrated voltage regulators, and electrochemical power delivery.

Schematic of stacked dies with dual-side cooling topology (source: IBM/IEDM)

Schematic of stacked dies with dual-side cooling topology (source: IBM/IEDM)

Session 4: Modeling and Simulation – Modeling and Simulation of Advanced Non-volatile Memory

Paper 4.1 is an atomistic (i.e., atom-by-atom) simulation of Ge-rich GexSe1-x materials for selector switches, coupled with experiment, so as to understand the electrical and thermal dynamics and correlate them to carrier-transport. They found that the population and localization of mobility-gap states changes solely under the effect of electric field. Nitrogen doping introduces strong covalent bonds into the material, increasing its thermal conductivity and crystallization temperature beyond 600C. Carbon dopants are found to add mobility-gap states, and nitrogen removes them.

Paper 4.2 also looks at atomistic simulations, this time of conductive bridging random access memory (CB-RAM) cells. Realistic device structures containing an atomic-scale filament have been constructed and their transport properties have been studied.
4.3 is another CB-RAM investigation, defining an active-electrode selection criterion for non-volatile and volatile switching; then simulating switching behaviour in Ag/HfO2/Pt and Co/HfO2/Pt, including the intrinsic switching time; and using this data to predict the switching behaviour of other CBRAM active-electrodes, and corroborate with experiments.

The disorder effect of oxygen vacancy distribution in filamentary analog RRAM is modeled in 4.4, and verified by experiments performed on a 1-Kb RRAM array, coming to the conclusion that disordered VO distribution is desired for analog switching.

In 4.5 we move on to 3D NAND flash memories, studying the charge diffusion in charge-trap (CT) cells, examining various hydrogen (H) and oxygen (O) incorporated defects in the SiN CT layer. The next paper (4.6) looks at wordline (WL) interference in a 32Gb 16-layer single-gate vertical-channel (SGVC) 3D NAND flash test chip, finding that the far-neighbour WL cell also contributes to the WL interference; this can be suppressed by applying a lower bitline sensing voltage.

The last talk (4.6) discusses the current transport through the thin polysilicon channel of (likely) Micron 3-D NAND flash strings, showing that variability in the polysilicon grain configuration in the channel broadens the array VT distribution when temperature is changed.


Session 5: Nano Device Technology — 2D and Carbon Nanotube Devices

This session (not surprisingly) is a set of research papers, starting with a trio of molybdenum disulphide (MoS2) transistor studies; 5.1 details gate-tunable memristors based on monolayer MoS2 grown by CVD, fabricated in a field-effect geometry with a polycrystalline MoS2 channel. In 5.2 high performance transistors with CVD graphene and MoS2 on commercially available paper substrates are demonstrated; and 5.3 exhibits a quantum dot superlattice structure fabricated on monolayer MoS2, where the quantum dots work as charge traps that induce memristive resistance, which can then be modulated by a gate-induced electric field and exhibits light stimulation.

In paper 5.4 electronic synapses were made using multilayer hexagonal boron nitride as a switching layer, showing the coexistence of volatile and non-volatile resistive switching.

Next is an invited talk on scaling carbon nanotube CMOS FETs towards the quantum limit (5.5) When combined with graphene, a high-performance top-gated CNT FET with gate length scaled down to 5 nm was demonstrated; this begins to touch the quantum limit of a FET, and involves approximately only one electron when switching between on-state and off-state.

Carbon nanotube FETs were fabricated based on solution-processed carbon nanotube film in 5.6. FETs with a gate length of 120 nm exhibited maximum drive current density of 1.7 mA/um and peak transconductance of 0.8 mS/um, which is claimed to create a new record for CNT FETs.

In the last paper, monolithic 3D-integrated dichalcogenide (MX2) FETs are benchmarked with Si FinFETs (5.7) using energy-delay as a figure-of-merit and a physical compact model. Single-gate (SG) and double-gate (DG) MX2 FETs are compared from ON current, device capacitance and energy-delay perspectives.


Session 6: Circuit and Device Interaction — Devices and Circuits for Neuromorphic and Stochastic Comparison

This topic is again covered by a set of research papers:

The first, 6.1, discusses NeuroSim+, an integrated simulation framework for benchmarking synaptic devices and array architectures in terms of system-level learning accuracy and hardware performance metrics; in particular, the impact of the “analog” eNVM non-ideal device properties, and benchmark the trade-offs of SRAM, digital and analog eNVM-based array architectures for online learning and offline classification.

A ferroelectric FET (FeFET) analog synapse for the acceleration of deep neural network training is demonstrated in 6.2. The symmetric 5-bit potentiation and depression characteristics of the FeFET synapse resulted in 90% accuracy for image recognition after training on the MNIST database, and improved training time on 1M images by 1000× compared to demonstrated RRAM devices is claimed, while maintaining a 10× area advantage over SRAM.

Paper 6.3 proposes Random Sparse Adaptation (RSA) to efficiently recover the accuracy due to RRAM variations. RSA integrates a small, accurate on-chip memory with the main, inaccurate RRAM array. It completely eliminates the Write of RRAM, achieving 10-100X speedup in MNIST and CIFAR-10, and >10% accuracy enhancement.

The time-dependent variability (TDV) in RRAMs, and its interaction with the RRAM-based analog neuromorphic circuits for pattern recognition is investigated in 6.4. It is found that the TDV effect can introduce non-negligible recognition accuracy drop during the operating condition. 6.5 details a mixed-signal neuromorphic network with 100K+ floating-gate memory cells, based on a commercial 180-nm NOR flash memory.

In paper 6.6, the feasibility of stochastic computing (SC) circuits based on FinFET technology is investigated, with on-chip image processing as an example. Practical technical issues are carefully examined, including static and transient device variations in 16/14nm FinFET.


Session 7: Characterization, Reliability and Yield — Reliability of Advanced Devices

Gate-all-around (GAA) nanowire (NW) devices are still a research topic to me, but the first paper in this session looks at the degradation of stacked Si gate GAA-NW nFETs (7.1), resulting in a fully intrinsic GAA-NW nFET lifetime map in the entire bias space.

In 7.2 we hear about hot carrier degradation (HCD) in FinFETs, studied from a trap-based approach rather than the carrier-based approach. A new HCD time dependence was observed, not predictable by traditional models, and from this a trap-based HCD compact model is proposed and verified in both n- and p-type FinFETs.

NBTI in replacement metal gate (RMG) HKMG SiGe p-FinFETs is modelled in 7.3; time kinetics for DC and AC stress and recovery, temperature dependence of voltage acceleration factor, and the impact of Ge% and N% are quantified, and benchmarked against Si p-FinFETs, and explained by TCAD and band structure calculations.

Paper 7.4 from imec discusses the impacts of device architecture, middle-of-line contact scheme, and S/D epitaxy process options on ESD diode performance in next generation bulk FF and GAA technologies, using 3D TCAD and ESD characterization.

Imec is back in 7.5, examining oxide traps in InGaAs MOS gate stacks in high-mobility n- channel MOSFETs. Various trap characterization techniques such as bias-temperature instability, defect capture-emission-time maps (applied here to InGaAs devices), random telegraph noise, hysteresis traces, and multi-frequency C-V dispersion, were used, on a variety of device test vehicles (capacitors, planar MOSFETs, finFETs, nanowires). They propose guidelines for developing sufficiently reliable III-V gate stacks.

A study of thermal effects in 3D sequential integration (CEA-leti’s CoolCube) is presented in 7.6, on 3D ICs made from 7nm-thick SOI wafers, with a base oxide thickness of 145nm. As we noted in 3.1, heat dissipation is an issue with monolithic stacking, because heat can negatively affect transistor electrical characteristics, performance and reliability. A particular area of concern is the need to understand the thermal effect of the second layer on the performance of devices in the first layer. The authors found that the self-heating of individual transistors is more significant than thermal coupling between the layers.

TEM image of two stacked transistors fabricated in 3D sequential integration technology (source: CEA-leti/IEDM)

TEM image of two stacked transistors fabricated in 3D sequential integration technology (source: CEA-leti/IEDM)

Session 8: Optoelectronics, Displays, and Imagers — Thin Film Transistors and Detectors

The first paper in the session presents an investigation (8.1) of flexible ultra-thin chalcogenide glass Ge2Sb2Te5 (GST) p-type thin-film transistors (TFTs). Together with n-type InGaZnO4, flexible CMOS inverters and NANDs are realized, and the devices sustain tensile bending to a radius of 6 mm.

The next paper (8.2) reports extremely stable and high performance etch-stopper a-IGZO TFTs on a plastic substrate by using split semiconductor and source/drain electrodes: the authors state that this technology can be used for the manufacturing of high resolution flexible AMOLED displays.

A printable device structure design is introduced in 8.3 to fabricate a low voltage organic field effect transistor, for low power and high sensitivity ion and fluorescence sensing, using thick gate dielectric layers and high throughput printing/coating processes.

A black phosphorus carbide infrared phototransistor with wide spectrum sensing is up next (8.4), which shows promise for IoT applications. It is followed by a paper discussing flexible paper deep UV photosensors (8.5) based on 2D BN nanosheets which have ultrahigh thermal conductivity, fast recovery-time, and excellent flexibility and bending durability.

A high-performance graphene/ultra-thin silicon metal-semiconductor-metal UV photodetector is reported in 8.6, which uses the mechanical flexibility and high-percentage visible light rejection of ultra-thin silicon. The proposed photodetector exhibits high photo-responsivity, fast time response, high specific detectivity, and UV/Vis rejection ratio of about 100, comparable to the state-of-the-art Schottky photodetectors.

A Schottky-PN cascade heterojunction short-wavelength infrared photodetector built with hyper-boron-doped silicon quantum dots on graphene is reviewed in the last paper (8.7).


Session 9: Power Devices — SiC and GaN Vertical Power Devices

This session alternates silicon carbide (SiC) and gallium nitride (GaN) papers – first up, Fuji Electric will present on a novel SBD-integrated SiC-MOSFET (9.1) with a small cell pitch; the fabricated 1.2 kV SWITCH-MOS successfully inactivated the body-PiN-diode without degradation of on- and off-state characteristics when compared with conventional UMOS.

In 9.3 Mitsubishi studied the intrinsic phonon-limited mobility and carrier transport properties of 4H-SiC MOSFETs, coming to the conclusion that surface roughness scattering does not limit inversion layer mobility in high effective normal field, suggesting that conventional mobility models need to be updated.

Schematic showing electron scattering in the inversion layer (source: Mitsubishi/IEDM)

Schematic showing electron scattering in the inversion layer (source: Mitsubishi/IEDM)

The SiC papers wrap up with an invited paper by Tsunenobu Kimoto of Kyoto U. (9.5) on “Progress and Future Challenges of SiC Power Devices and Process Technology” We can expect a review of recent progress in SiC device physics and power devices, more accurate device simulation of SiC, and details of 13 kV SiC PiN diodes ,11 kV SiC epitaxial MPS diodes, and 3 kV reverse-blocking MOSFETs.

9.2 demonstrates a 1200 V GaN vertical finFET with claimed record performance in a normally-off GaN vertical transistor with submicron fin-shaped channels; the figure of merit is up to 7.2 GW/cm2. A >1.4 kV OG-FET with a novel double field-plated geometry is detailed in 9.4, with a breakdown voltage of 900 V and an on-state resistance of 4.1 ohm.

The final GaN paper, 9.6, looks at high voltage vertical p-n diodes with ion-implanted edge termination and sputtered SiNx passivation. These are GaN-on-GaN diodes with a Baliga figure of merit of 13.5 GW/cm2, and do not require field plates or complex edge terminations to achieve material-limited performance.


Session 10: Focus Session – Sensors, MEMS, and BioMEMS — Nanosensors for Disease Diagnostics

Being a focus session, again we have a series of invited papers, starting with a review of nanofluidics for cell and drug delivery (10.1). Houston Methodist has developed implantable micronanofluidic-based platforms that leverage molecular nanoconfinement for the controlled administration of drugs and transplantation of cells using silicon nanofabricated membranes and 3D-printed polymeric architectures.

Photo and schematic of the internal structure of the Houston Methodist remote-controllable drug-delivery platform (source: Houston Methodist/IEDM)

Photo and schematic of the internal structure of the Houston Methodist remote-controllable drug-delivery platform (source: Houston Methodist/IEDM)

I tend to think of bulk acoustic wave (BAW) resonators as filters in mobile phones, but Tianjin U. has been developing them as biosensors and bioactuators (10.2). This review
covers two aspects, as biosensors to provide label-free measurement of biomarkers, and as bioactuators to manipulate biomolecules and enhance biosensing performance.

10.3 details a microfluidic device from Nagoya U., based on ionic current detection for single bacteria and mammalian cell sizing. A highly precise sizing system based on blocking ionic current at a narrow microchannel provided information on antibiotic-resistant strains of bacteria; and deformability changes associated with the passage of adipose tissue-derived stem cells (ASCs) were also successfully detected without any chemical or biological modification.

The next paper (10.4) from Seoul National U. describes a rapid antibiotic susceptibility test (RAST) system composed of biochips and an automated expert system, which can determine the antibiotic susceptibility of bacteria and mycobacteria derived from various parts of the body. With RAST, antibiotic susceptibility was available in six hours, versus conventionally taking more than two days.

In 10.5 Reza Mohamadi from U. Toronto next describes the microscale profiling of circulating tumor cells (CTCs), which are potential cancer markers; they are heterogeneous and can change as they enter the bloodstream, so profiling them at single cell level is critical to unraveling their complex and dynamic properties. This paper discusses new nanoparticle-enabled microscale technologies for CTC classification, which characterizes them based on their surface expression profile.

Cancer is also the subject of 10.6, from multiple institutes of the Grenoble research complex, which discusses encapsulated organoids and an organ-on-a-chip platform for cancer modeling. An example is given of “prostate-on-a chip” developments to illustrate the potential of engineered organ-on-chip devices for creating novel human organ and disease models.

A team from U. British Columbia (10.7) have developed a microfluidic flow-focusing method to create multicellular, 3-D spheroids that can better model several aspects of a tumour in vivo, including diffusion gradients of O2 and drugs. This drives the need to image deep within the tissues to assess parameters such as cell viability at the tissue cores, or drug penetration into the tissue as a function of time. They developed an on-chip method to rapidly clear arrays of 3-D cell cultures and micro-tissues, compatible with two-photon microscopy to track drug and nanomedicine penetration into the tissues.

That brings us to the end of the Monday afternoon sessions, and the reception will start at 6.30 pm in the Grand Ballroom.



Session 11: Focus Session – Memory Technology — Modelling Challenges for Neuromorphic Computing

Again, all invited papers – the session starts (11.1) with a discussion from UC Irvine on “Stochastic Synapses as Resource for Efficient Deep Learning Machines”; it is shown that always-on stochasticity at networks connections is a sufficient resource for deep learning machines, when combined with simple threshold non-linearities. The findings can improve performance of deep learning machines with fixed point representations, and argue in favor of stochastic nanodevices as primitives for efficient deep learning machines.

Paper 11.2 presents a summary of recent results toward implementing RRAM-based attractor networks. Using realistic models of HfO2 RRAM devices, recurrent networks were designed and simulated, showing the capability to train, recall and sustain attractors; this supports the feasibility of RRAM-based bio-realistic attractor networks.

The next talk (11.3) comes from a different angle – studies of the human brain show that synapses in the brain do not maximise information transfer, but instead transfer information in an energetically efficient manner. This implies a high failure rate in the transmission of individual information-carrying signals, which may be an important design principle when considering trade-offs between energy use and information transfer in man-made devices.

11.4 reviews the understanding of the trade-offs of device, circuit and application in ReRAM-based neuromorphic computing systems, through the discussion of three major problems — weight mapping, reliability, and system integration.

We again consider RRAM in 11.5; the device structure and materials stack detailed in the paper were optimized to achieve reliable bidirectional analog switching behavior. A human face recognition task was demonstrated on a 1k-bit 1T1R RRAM array using an online training perceptron network, and several RRAM characteristics were carefully evaluated for a handwritten digit recognition task.

Paper 11.6 also highlights the feasible routes of using RRAM for accelerating online training of deep neural networks (DNNs). Highly accurate online training could be realized using simple binary RRAMs that have already been widely developed as digital memory.

We go to the atomic level in last talk in the session (11.7), which discusses a modeling platform connecting atomic material properties to electrical device performance, in relation to neuromorphic computing devices. The main ingredients of the platform are reviewed considering the different technologies (e.g. RRAM, PCM, FTJ) proposed for 3D-integrated neuromorphic computing.


Session 12: Circuit and Device Interaction — Circuit-Device Challenges in More Moore and More than Moore

Paper 12.1 details twin-mode non-volatile logic gates that allow multiple logic functions to be obtained by controlling its non-volatile states, that are fabricated in a standard 16-nm FinFET process. The floating metal-gate based cells consist of an inverter controlled by slot contact.

Physical unclonable functions (PUFs) are considered in 12.2. Here we have a new PUF design based on a double-layer RRAM array architecture and digital RRAM programming, achieved by splitting resistance distribution after a continuous distribution was formed. It was implemented on a 16 Mb RRAM test chip, and its randomness was verified with a NIST test suite, and demonstrated strong reliability and significantly enhanced resistance against machine-learning attack.

12.3 is an invited paper from MIT – “Large-Scale Terahertz Active Arrays in Silicon Using Highly-Versatile Electromagnetic Structures”. The small wavelength of terahertz (THz) signals and the high integration capability of silicon processes make it possible to build a high-density, very-large-scale active THz array on a single chip. There are problems though; most conventional circuit designs are area-inefficient, leading to unnecessarily large chips.

MIT has designed a set of compact while versatile circuits, using structures with tight device-electromagnetic integration that exhibit multi-mode behaviors. Put on silicon, that can achieve homogeneous arrays for high-power, collimated radiation, or alternatively, heterogeneous arrays for fast broadband spectral scanning. They demonstrate an example with 0.1-mW power generation (20-mW effective isotropically-radiated power) at 1 THz, simultaneous transmit/receive capability, and high-parallelism molecular spectroscopy.

Peking U. gives another invited talk in 12.4 about variability- and reliability-aware design for 16/14nm (and beyond) technologies. Accurate compact models and a new design methodology for random variability in FinFETs are proposed for the variation- and correlation-aware design.

For the reliability awareness, the impacts of BTI-induced temporal shift and the layout dependent aging effects should be taken into account for the optimization of end-of-life (EOL) performance/power/area (PPA). A new-generation aging model and circuit reliability simulator for FinFETs are also proposed and developed in industry-standard EDA tools.

TSMC discusses (12.5) a bit-level characterization method for benchmarking finFET SRAM performance under the influence of leakage current; whether it be due to intrinsic or extrinsic device failure, it can severely impact the 6-T SRAM performance. This study introduces a ‘Pseudo-Leakage’ current source in the SRAM circuit and analyzes the impact on the overall SRAM performance matrices.

Computing-in-memory (CIM) is becoming a hot topic now that memory interfaces have become the data bottleneck in systems; paper 12.6 describes a monolithic 3D vertical cross-tier computing-in-memory SRAM cell, fabricated using a low cost TSV-free FinFET 3D+-IC technology. The 9T 3D CIM SRAM cell is able to compute NAND/AND, OR/NOR and XOR/XNOR operations within a single memory cycle.

The stackable, multi-fin, single-grained Si FinFET was fabricated using low thermal-budget CO2 far-infrared laser annealing (FIR-LA) for activation, and self-aligned silicide. This monolithic 3D device reduces area overhead by 51%, compared to the 2D version, thanks to the stacking of three additional transistors above the 6T SRAM cell.


Session 13: Modeling and Simulation — Modeling and Simulation of Advanced CMOS Transistors

In 13.1 hot-carrier degradation (HCD) in FinFETs is analyzed. A physics-based HCD model was used to study the distribution of the trap density across the fin/stack interface, after experimental validation. The effect of fin length, width, and height on HCD was analyzed, showing that HCD is worse in shorter and wide-finned devices, with little impact from fin height.

13.2 is a comparison of FinFETs, stacked nanowires (NWs), circular and square gate-all-around 𝑛-FETs, using a deterministic BTE solver that accounts for quantum confinement, a wide set of scattering mechanisms and self-heating. Surface roughness is shown to reduce the improvement in I𝑜𝑛 expected in stacked NWs compared to FinFETs, and whether or not In0.53Ga0.47As can provide better I𝑜𝑛 than strained silicon.

Monte Carlo benchmarking of FinFETs with LG 20, W 9 nm shows that InGaAs has similar performance as Si for Vdd of 0.5 V (13.3). However, ideal InGaAs-FinFETs lose all advantage upon reducing W to 5 nm because of a charge reduction due to n-type channel doping.

13.4 is an invited review paper, looking at modelling nanoscale n-MOSFETs with III-V compound semiconductor channels, from advanced models for band structures, electrostatics and transport to TCAD. 13.5 discusses a ferroelectric transistor model for FEFETs/NCFETs without an inter-layer metal between ferroelectric and dielectric in the gate stack.

The final paper (13.6) considers self-heating effects (SHE) in FinFETs, NWFETs, and nanosheet-FETs. The IC-specific SHE reflects increasing thermal resistances (Rth) associated with the transistor, circuit, and system of the hierarchy. Physics-based compact models are developed for each tier, then stacked to estimate junction temperature-dictated performance/reliability of sub-10nm technologies. The authors concluded that nanosheet-FETs are good candidates at sub-10nm nodes, with a lower subthreshold swing than FinFET, and better reliability than NWFET.


Session 14: Process and Manufacturing Technology — Interconnect Patterning and Memory Integration

The first paper is a trip down memory lane by Dan Edelstein of IBM (14.1), marking the 20th anniversary of the introduction of copper interconnect into the metal/dielectric stack of ICs. Twenty years ago, Dan presented at IEDM ’97:

fig 7


With the accompanying colorized cross-section:

cross section
Copper interconnect is now in its 10th generation of manufacturing, and 12th in research, but as we will see in Intel’s paper (29.1), cobalt is being used in their 10-nm process, so copper may have run its course in leading-edge technologies.

The second talk is by one the Albany consortia (14.2), detailing a fully aligned via BEOL integration scheme at 36 nm pitch, with claimed extendibility to beyond the 7-nm node. We get exotic in 14.3, with an all-carbon interconnect scheme that integrates horizontal multilayer graphene wires and vertical carbon-nanotube vias. It is reported that it surpasses copper in terms of performance, energy efficiency, and reliability down to the 5-nm node.

After the coffee break Bob Turkot of Intel gives an invited talk on “Continuing Moore’s Law with EUV Lithography” (14.4), reviewing the current status and challenges of EUV lithography for high volume manufacturing. Source power is now up to 250W, and throughput is >125 wafers/hr, so “insertion” is anticipated in the next year, and Samsung claims it will using EUV for its 7-nm generation.

Now that we have cobalt interconnect going into production, it needs to be inspected, and Applied Materials is up next (14.5), describing a non-destructive electron beam cobalt void detection method. This uses an improved SEM imaging technique that is shown to correlate the electron signal to the volume and depth of voids in the metal.

The last presentation (14.6) switches to memory, discussing the improvement of HfO2-based RRAM performance by local Si implantation; this is claimed to enable switching area localization, and to significantly decrease forming, set and reset voltages, and improving data retention, while not being detrimental for endurance.


Session 15: Nano Device Technology — Negative Capacitance and Other Steep-Slope Devices 1

First up in this session (15.1), GLOBALFOUNDRIES discusses a “14nm Ferroelectric FinFET Technology with Steep Subthreshold Slope for Ultra Low Power Applications”. Here they have integrated doped hafnia ferroelectric layers into their 14nm FinFET technology, without any further process modification, and demonstrated ring oscillators operating at frequencies similar to regular dielectrics, while improved subthreshold slope reduces their active power.

Ferroelectric negative capacitance finFETs are investigated using transient TCAD simulation in 15.2; the proposed FinFETs are expected to operate at 0.25 V and thus are promising for low-power applications. The first hysteresis-free Ge CMOS FinFETs are reported in 15.3, exhibiting sub-60mV/dec subthreshold slope (SS) in both forward/reverse sweeps at room temperature with ferroelectric Hf0.5Zr0.5O2 (HZO) and Al2O3/GeOx.

15.4 discusses Ge NWFETs with a HfZrOx ferroelectric gate stack, exhibiting SS <60 mV/dec and examining biasing effects on ferroelectric reliability; and 15.5 is an investigation of the frequency dependence of performance in Ge negative capacitance (NC) pFETs.

Next is a proposal and demonstration of an oxide-semiconductor/(Si, SiGe, Ge) bilayer tunneling field effect transistor (15.6), and in the last paper (15.7) we hear about crystal-oriented black phosphorus TFETs with transport directions aligned to the armchair and zigzag crystal orientations. Strong band-to-band- tunneling anisotropy is observed between the two orientations, with a subthreshold slope nearing the thermionic limit of 22 mV/dec at 110 K.


Session 16: Optoelectronics, Displays and Imagers — Image Sensors and Single-Photon Detectors

Sony is a dominant force in image sensors, and they start this session with a description of a CMOS image sensor (CIS) photon-detector targeted on replacing photo multiplier tubes (16.1). 15-µm pitch active sensor pixels with complete charge transfer and readout noise of 0.5 e- RMS are arrayed, and their digital outputs are summed to detect micro light pulses. Successful proof of radiation counting is demonstrated.

16.2 also details a radiation imaging device, this time using SOI pixel technology. Issues of the back-gate effect, coupling between sensors and circuits, and the TID effect have been solved by introducing a middle Si layer. A small pixel size is achieved by using the PMOS and NMOS active merge technique.

Next we have a report (16.3) on a backside-illuminated germanium-tin (GeSn) large-area, tensile-strained and single-crystal photodiode array, formed on a quartz substrate by using laser-induced liquid-phase crystallization. Since quartz is transparent to NIR frequencies, and is compatible with silicon, GeSn near-infrared (NIR) imagers could be integrated with silicon CMOS circuitry.

Sony continues the NIR theme in 16.4, demonstrating NIR sensitivity enhancement of back-illuminated CIS by forming pyramid surface structures on crystalline silicon and using deep trench isolation (DTI). The diffraction on the pyramids results in a quantum efficiency of more than 30% at 850 nm. Using a special treatment process and the DTI, without increasing the dark current, the amount of crosstalk to adjacent pixels was decreased, providing resolution equal to that of a flat structure.

STMicroelectronics has succeeded in getting their SPAD (single-photon avalanche diode) technology into the iPhone 7 and 8 series, and the iPhone X, and in 16.5 they report pushing into the 40-nm node; a high fill factor >70% is claimed, a low dark count rate (DCR) median of 50 cps at room temperature and a high photon detection probability (PDP) of 5% at 840 nm, as well as the potential to 3D-stack the device.

A back-illuminated 3D-stacked SPAD using 45-nm CMOS is shown next (16.6). This has a DCR of 55.4cps/µm2, and a maximum PDP of 31.8% at 600nm, over 5% in the 420-920nm wavelength range.


Session 17: Compound Semiconductor and High Speed — 1D and 2D III-V Nanoscale MOSFETs
This session is where we get to hear more about vertical nanowires (VNWs) and other exotica. That’s what we have in 17.1, where high performance, dry etched In0.53Ga0.47As vertical nanowire and nanosheet devices are reported, fabricated using a VLSI compatible flow.

Left: TEM cross-section of the width of a 37x480nm single nanosheet FET device Right:TEM of vertical nanowire resistor after transmission line measurement (TLM) fabrication (source:  IEDM/KU Leuven/imec)

Left: TEM cross-section of the width of a 37x480nm single nanosheet FET device Right:TEM of vertical nanowire resistor after transmission line measurement (TLM) fabrication (source: IEDM/KU Leuven/imec)

More InGaAs VNWs are detailed next (17.2), fabricated by a top-down approach using reactive ion etching, alcohol-based digital etch and Ni alloyed contacts. Record ON current and peak transconductance are obtained in a 7-nm diameter device. Excellent scaling behavior is observed with performance increasing as the diameter is shrunk down to 7 nm.

17.3 considers sub-100-nm gate-length scaling of InAs/InGaAs VNWs on silicon with gate-lengths ranging from 25 to 140 nm. The heterogeneous integration of InGaAs MOS-HEMTs and Si-CMOS on 200 mm wafers is discussed in 17.4; the HEMT epitaxial layers, with threading dislocation density of lower than 2 × 107 cm-2 are demonstrated using MOCVD and an effective mobility of 4900 cm2/V·s at sheet carrier density of 3 × 1012 cm-2 is achieved.

A scaled replacement-metal-gate InGaAs-on-Insulator n-FinFET on Si is detailed next (17.5), and 17.6 has self-aligned InGaAs FinFETs with 5-nm fin-width and 5-nm gate-contact separation fabricated through a CMOS compatible front-end process. Precision dry etching of the recess cap results in metal contacts that are about 5 nm away from the intrinsic portion of the fin. The last paper demonstrates an InGaSb p-channel FinFET (17.7) with a narrowest fin width of 10 nm, a gate length of 20 nm, and a fin width/channel thickness aspect ratio > 2. To fabricate the devices, a new antimonide-compatible digital etch was developed.


Session 18: Sensors, MEMS, and BioMEMS — Bio and Chemical Sensors

The first paper describes a Lab-on-Skin that is a fully integrated, low-power, multi-sensing smart system that can passively collect sweat and measure its biomarker content in real-time, from a team led by EPFL (18.1). It is built using wafer-level techniques, and features the 3D-stacking of ion-sensitive, fully depleted SOI (FD SOI) FETs and micro/nanofluidic sensing channels created with the commonly used SU-8 negative photo resist.

Schematic of Lab-on-Skin; the two top layers depict the design of the sensing and microfluidic layers, while the bottom layer is a wafer-level view after the ion-sensitive FETs and the first layer of SU-8 passivation have been fabricated.  (source: IEDM/EPFL)

Schematic of Lab-on-Skin; the two top layers depict the design of the sensing and microfluidic layers, while the bottom layer is a wafer-level view after the ion-sensitive FETs and the first layer of SU-8 passivation have been fabricated. (source: IEDM/EPFL)

18.2 presents a strategy to design and fabricate a skin-like nanostructured biosensor system for non-invasive blood glucose monitoring. 18.3 details a mechanical-field-coupled thin-film transistor (TFT) intended for mechanical sensor applications. A tactile sensor was demonstrated with high sensitivity that can detect a gentle dynamic touch down to mN, and a wearable piezoelectric self-driven heart rate monitoring device with only µW-range power consumption.

The study in 18.4 presents a wearable and flexible temperature sensing circuitry for a diagnosis of skin temperature. The system is based on a carbon nanotube (CNT)-based temperature sensor array, built on cotton yarn using a mixture of multi-walled (MW)-CNTs and PDMS (polydimethylsiloxane). To divide and select the unit thermistors, a normally-off memristor was used.

18.5 describes a monolithically integrated Si-CMOS-monolayer-graphene gas sensor, joining the two-dimensional material with low latency, low power, low-cost silicon CMOS. Fujitsu has developed a two-dimensional SnS2-based gas sensor in 18.6. It can detect HCHO, a gas causing “Sick Building Syndrome,” with concentrations down to 1ppb.

These seven sessions take us to lunchtime when, instead of the usual Conference Luncheon, we have the IEDM Entrepreneurs Luncheon in Continental 4 ballroom, featuring Courtney Gras, Executive Director for Launch League, a local nonprofit focused on developing a strong startup ecosystem in NE Ohio.


Session 19: Memory Technology – Charge Based Memories and Advanced Memories
A 128Gb (MLC)/192Gb (TLC) Single-Gate Vertical Channel (SGVC) architecture 3D NAND is described by Macronix (19.1) using only 16 layers. It makes use of arrays of vertically arranged single-gate, flat-cell thin film transistors with an ultra-thin body, which aren’t as sensitive to CD variation as the industry-standard GAA devices. SGVC has the important advantage of much smaller cell size and pitch scaling capability which allows very high-density memory at much lower stacking layer number.

Schematic diagram illustrating the advantages of the SGVC flat-channel device  (source: IEDM/Macronix)

Schematic diagram illustrating the advantages of the SGVC flat-channel device (source: IEDM/Macronix)

TEM cross-sectional views in the (left) channel length and (right) width directions  (source: IEDM/Macronix)

TEM cross-sectional views in the (left) channel length and (right) width directions (source: IEDM/Macronix)

In 19.3 Renesas has managed to adapt the split-gate flash structure to the finFET structure, presumably sourcing from TSMC and Samsung since they mention 14- and 16-nm processes. A finFET SG-MONOS eFlash array is successfully operated and tight Vth distribution is confirmed, even after retention. This paper raises some questions in my mind – have they converted it to replacement metal gate? Do we have the fin etch-back and epi growth? This should be interesting…

GLOBALFOUNDRIES has been publicizing their MRAM recently, and 19.7 is a presentation on that very topic from their Dresden fab. They show a ferroelectric field effect transistor (FeFET) based eNVM solution for a 22nm FDSOI CMOS technology (22FDX). FeFET cells are aggressively scaled to 0.025 μm² with memory windows of 1.5V, and endurance up to 10E5 cycles.

Schematic of eMRAM cell  (source: GLOBALFOUNDRIES)

Schematic of eMRAM cell (source: GLOBALFOUNDRIES)

Session 20: Circuit and Device Interaction – Path-Forward for Advanced CMOS Scaling

This session starts with an Intel paper on interconnect scaling (20.1) which as we know is a key performance limiter instead of the transistors. They show a 35% performance improvement obtained by device-circuit-architecture solutions, using reconfiguration of buffered interconnects and execution architecture.

20.2 is from GLOBALFOUNDRIES, discussing the benefits, trade-offs and limitations of aggressive fin width scaling down to 1.6 nm on logic and SRAM device characteristics, and also considering an AC performance boost opportunity from gate length scaling along with fin width scaling.

In 20.3, it looks as though CEA-Leti is studying the possible double-gate operation of the top transistor in a monolithic 3D stack, and they have done extensive layout and spice simulations of standard cells and SRAMs.

Imec continues reporting on their nanosheet technology (20.4), showing 5.5-track standard cells with gate pitch of 42 nm and metal pitch 21 nm. They demonstrate that three stacked nanosheets are competitive with FinFETs made with two fins, while relaxing the constraints on design rules.

20.5 is another imec nanosheet paper; “Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm”. It discusses SRAM scaling beyond the 5nm technology node, and highlights the fundamental scaling limits due to FinFET and GAA technology. A vertically stacked lateral nanosheet architecture using a forked gate structure is proposed, showing superior performance and area scaling with limited additional processing complexity.

Georgia Tech updates Rent’s power-law (20.6), addressing the inability of the current approach to accurately capture standard cell level, and design characteristics that are inherent to the way we design microprocessors today. The proposed models are validated against state-of-the-art commercial microprocessors at 14/16nm, 10nm and 7nm process nodes, and the results illustrate the importance of design-specific technology prediction.


Session 21: Characterization, Reliability and Yield – Memory Reliability

TSMC presents (21.1) on the effect of external magnetic fields on embedded perpendicular STT-MRAM technology qualified for solder reflow. They show that the most critical polarization direction is writing from a parallel to an anti-parallel state, with an external field opposed to both the final free layer direction and the bottom pinned layer direction. Various other key factors including temperature, write condition and MTJ film stack were also studied.

In 21.2, an epi-Si process is used to investigate the impact of traps and grain boundaries in vertical 3D NAND. The defects are shown to have a reduced impact on device performances compared to the usual poly-Si channel devices. These results are also confirmed and extrapolated to other geometry using 3D TCAD simulations.

Now that 3D NAND is in volume production, we are starting to see more detailed reliability studies. In 21.3, Micron examines the impact of temperature on RTN fluctuations in 3D NAND flash cells. The average amplitude of RTN fluctuations increases when temperature is reduced. This is explained by TCAD simulations, in terms of stronger nonuniformities in the polysilicon channel inversion at lower temperatures, increasing the dVT of traps at or close to the polysilicon grain boundaries.

In 21.4 a physical mechanism for random-telegraph-noise (RTN) in oxide based resistive switching memory (Ox-RRAM) is proposed, with the new insight that current fluctuation can be attributed to the activation and deactivation of oxygen vacancies (VO) in the filament gap region. A RTN-based VO probing method is proposed to analyze the properties of each VO and detect the VO count in the filament gap region, and can establish a connection between the microcosmic VO properties and the Ox-RRAM reliability. The tail bits of high resistance state are shown to originate from the redundant VO generation in the filament gap region in the ineffective RESET phase, and an optimized operation scheme is presented to suppress the tail bits.

IBM Research gives an invited review of the fundamental limitations of existing models and future solutions for dielectric reliability and RRAM applications (21.5) The Weibull/ Poisson model and constant field-acceleration E-model are useful for more-or-less ideal situations, but new applications and experimental findings have challenged and exposed the fundamental limitations of these decades-old models. Recent advances in atomistic simulation and microscopic modeling provide fresh insights for the correct choice of field/voltage acceleration models.

SK Hynix details reliability improvement in DRAMs (21.6) by using a silicon migration technique by hydrogen annealing after a dry etch to form the saddle-fin structure in a 2y-nm 4Gb DRAM. The anneal reduces the interface trap density, enhancing the variable-retention-time and row-hammering immunity. Now that we are into the 10-nm class, this is likely to be even more important; at last year’s IEDM, a SK Hynix spokesman said that he hoped to get four nodes out of the 10-nm, and most road-maps I’ve seen have at least three.


Session 22: Process and Manufacturing Technology – Advanced Metal Gate and Contact Technology

The IBM/Samsung/GLOBALFOUNDRIES trifecta kicks off the session with a look at VT tuning in stacked nanosheet gate-all-around (GAA) transistors (22.1). VT can be modulated through work-function metal (WFM) thickness as well as the inter-nanosheet spacing (Tsus); combining the two can increase the number of undoped VT offerings.

If you believe Applied Materials (22.2), RMG gate fill will be using cobalt, in a reflow process, combined with a thin barrier layer for future node FinFET and gate-all-around technology.

IBM/GLOBALFOUNDRIES details a manufacturable CMOS dual solid phase epitaxy (SPE) process in 22.3, on both NFET and PFET in a 7-nm technology. Contact resistivity is reduced by both the conventional approach of high in-situ doped epi and the novel SPE processes.

22.4 is a comprehensive study of Ga activation in Si, SiGe and Ge. A low Ti/p-Ge contact resistivity of 1.2×10-9 ohmic·cm2 is approached using Ga doping and low temperature activation, while a record-low contact resistivity for p-Ge down to 5×10-10 ohmic·cm2 with a high activation level of 5×1020cm-3 is achieved using nanosecond laser activation.

22.5 Cluster-Preforming-Deposited Amorphous WSin (n = 12) Insertion Film of Low SBH and High Diffusion Barrier for Direct Cu Contact

In 22.5, the insertion of WSi12 films reduces the Schottky barrier height to 0.32 eV at W/n-Si and to 0.51 eV at W/Ge/p-Si junctions. It also extends TDDB lifetime to >10 years at 100ºC under 5 MV/cm stress for Cu MOS capacitors, potentially enabling direct Cu contacts at S/D in advanced CMOS.

Session 23: Nano Device Technology – Negative Capacitance and Other Steep-Slope Devices 2

The scaling potential of negative capacitance FinFET and FDSOI (NC-FinFET and NC-FDSOI) are studied for technology nodes down to 2nm (23.1). TCAD simulation evidence is presented that negative capacitance enables FinFET and FDSOI scaling to the 2 nm node, showing Ioff < 100nA/um and 10%~29% higher Ion compared with 2nm FinFETs and FDSOI. Also, NC-FDSOI exhibits similarly strong back-gate bias effects on Ioff and Ion compared with FDSOI.

In 23.2, HfAlOx NCFETs with gate strain exhibit 66% Ion enhancement and 27% Vt reduction. Additional defect passivation can mitigate the interface depolarization field and help to reinforce surface potential amplification effect.

Ferroelectric Al:HfO2 NCFETs are demonstrated (23.3) with SS of 40 mV/dec and 39 mV/dec for forward and reverse sweep, respectively.

23.4 is an investigation of the physics and technology of the electronic insulator-to-metal transition (E-IMT) effect to create predictive model showing that, for reliable operation, the maximum ON/OFF ratio of an E-IMT device should follow a square-root relation with the strength of the thermally driven insulator-to-metal transition (T-IMT).

It was verified by systematic experiments using prototypical VO2 E-IMT devices, achieving a record value of reliable E-IMT with an ON/OFF ratio of 3.5×103 at 1.2 V, more than 10x improvement over the previous state-of-the-art. A record low voltage of IMT switching at 0.3 V (ON/OFF ratio =20) was also demonstrated.

Steep-slope MoS2 NC-FETs with ferroelectric HZO and IMG are demonstrated in 23.5. SS less than 50 mV/dec is obtained for both forward and reverse gate voltage sweeps, with minimum SSFor=37.6 mV/dec and SSRev=42.2 mV/dec. The impact of parasitic capacitance on SS and dynamic hysteresis is systematically studied by both experiment and simulation.

A high-performance and low-power MoS2 NCFET is demonstrated in 23.6, with ultra-low subthreshold swing (SS) of 23 mV/dec, sub-60 mV/dec over 6 orders of ID, nearly hysteresis-free, small |Vth|

A NbO2 based threshold switch device is detailed in 23.7; the NbO2 threshold switching (TS) device is connected in series with the gate side of a MOSFET. Thanks to the TS device showing an abrupt transition between the OFF and ON states at threshold voltage (Vth), the implemented transistor exhibits extremely low leakage current (10-7μA/ μm), high ION/IOFF ratio (>106), sub-2 mV/dec subthreshold swing, drift-free characteristic and high temperature operation (>85°C). The Vth is also tunable by controlling the thickness of the NbO2 TS device, so the NbO2-MOSFET can fulfill various demands of operating bias conditions.


Session 24: Optoelectronics, Displays and Imagers – Silicon Technology Based Optoelectronics

As we noted earlier (16.5), STMicroelectronics has penetrated the iPhone bill of materials with their time-of-flight sensors, which have a VCSEL mounted on the die; the next step is to integrate the laser into the CMOS platform, now detailed in 24.1 in a joint paper from U. Grenoble Alpes and STMicroelectronics. They show the integration of a hybrid III-V/Si laser into a fully CMOS-compatible 200mm technology; the fabrication flow is fully planar and compatible with the large-scale integration of silicon photonics circuits.

24.2 is an invited talk discussing direct bandgap group IV materials, GeSn/SiGeSn heterostructures and resulting quantum confinement effects for laser implementation. The 32-nm SOI process from (I guess) GLOBALFOUNDRIES is used by UCal and MIT (24.3) to demonstrate a monolithic silicon photonic platform in an unmodified 32nm SOI CMOS process. This platform provides the fastest transistors ever monolithically integrated with photonics.

A Ge based, steep switching (114 mV/dec), directly tunnel-modulated LED/laser light source (Germanium Zener-Emitter) and sub-thermal voltage-switching (31 mV/dec) photodetector (Germanium Esaki-Collector) is reported in 24.4, for the potential monolithic integration of an optical transceiver on silicon (100).

A 25 Gbps electro-optic Pockels modulator is integrated on to silicon (24.5); the devices, based on barium titanate thin films on 200 mm wafers, show excellent VpiL (0.3 Vcm) and VpiLa (1.7 VdB), high-speed operation (25 Gbps), and low static power tuning (100 nW).


Session 25: Power and High-Speed Devices – Novel Device Concepts

In the first paper, led by Panasonic (25.1), high current and high voltage AlGaN/GaN MIS-HFETs on Si are demonstrated, with a drain current of 20 A and breakdown voltage of 730 V, serving normally-off operations; the devices use an AlON gate insulator.

Next, in 25.2, a normally-off power switching device with interdigitated MIS-HEMT and lateral-SBD sharing common ohmic contacts and access regions is described, exhibiting a Vth of 1.7 V, RON of 12.1 Ω•mm, BV of 698 V, and reverse turn-on voltage of 0.6 V.

Paper 25.3 demonstrates improvement of the linearity of GaN-based high electron mobility transistors (HEMTs) through VT- engineering and self-alignment through channel-fin-formation. Lateral diamond MOSFETs operating in the deep depletion regime have been experimentally demonstrated in 25.4, exhibiting already impressive features: 200 V breakdown with 0.6 nA/mm gate and drain leakage, 4 MV/cm peak electric field at breakdown even without the use of field plates, and carrier mobility between 1000 and 1700 cm²/V.s.

In 25.5 NXP shows off a new 5V-EDMOS device (BV ~ 10V) comprising a stepped gate oxide and a dummy gate, which boosts the RF performance to a record fMAX (~ 450 GHz), very high fT (~ 90GHz) and small device degradation, fabricated in a baseline 40-nm CMOS technology.

We don’t often see filter technology at IEDM , but every mobile phone has them; here (25.6) Akoustis Technologies reports on a high-rejection 5.2-GHz wideband bulk acoustic wave filter using undoped single crystal AlN-on-SiC resonators. The filters had an absolute 4dB bandwidth of 151 MHz, a minimum insertion loss of 2.82 dB and rejection >40 dB. Resonators show k2eff of 6.32%, Q of 1523, and FOM of 96.


Session 26: Sensors, MEMS, BioMEMS – Technologies for Neural Activity Monitoring and DNA Analysis

In 26.1, low impedance transparent graphene microelectrode arrays are fabricated for artifact-free electrophysiological recordings. Transparent graphene electrodes eliminate light-induced artifacts during optical imaging and optogenetic stimulation.

A passive Si photodiode array, aiming to establish a miniaturized optical recording device for in-vivo use is described in 26.2. The array features high yield (>90%), high sensitivity (down to 32 μW/cm2), high speed (1000 frame per second by scanning over up to 100 pixels), and sub-10uW power.

26.3 reports that arrays of vertical gallium phosphide nanowires are promising materials for biosensing in membranes and cells. Additionally, nanowires were used to investigate the interactions of high aspect ratio nanoparticles with living cells and tissue.

The integration of FinFETs and 3D nanoprobes devices on a common bio- platform is discussed in 26.4, for monitoring the electrical activity of single neurons.

The direct characterization of cell-free DNA (cfDNA) in blood plasma using µLAS technology (26.5) allows the quantification of the size distribution of purified cfDNA in a few minutes, even when its concentration is as low as 1 pg/µL. It is also shown that DNA profiles can be directly measured in blood plasma, to speed up the cfDNA analytical chain.

26.6 details nanopore devices integrated with ITO gate electrodes, that are used for electrical gating of DNA at different folding states; pore diameters are <10nm and lengths ~30nm. The gate bias modulates the DNA translocation, and as VG goes from
-0.5V to 0.5V, the count of folded-once events increases by ~5.5X relative to that of unfolded ones, indicating electrical modulation of the effective pore cross-section.


After the sessions finish Applied Materials will be having their usual IEDM off-site gathering, at the Parc 55 hotel at 5 pm, and Coventor is also hosting a panel discussion in the Hilton, also at 5 pm.


Session 27: IEDM Evening Panel

Instead of the usual two competing panels, we have one panel this year, moderated by Philip Wong of Stanford; tentative panelists are Kaizad Mistry (Intel), Kevin Zhang (TSMC), Jong Shik Yoon, (Samsung), Chidi Chidambaram (Qualcomm), Kazu Ishimaru, (Toshiba Memory), TY Chiu (SMIC), and Hughes Metras (CEA-LETI). The topic will be “Where will the next Intel be headquartered?”. Despite the focused title, this is intended to be a wide-ranging discussion on the future of the semiconductor industry and how it could evolve in the next ten years.

Stay tuned for more preview of IEDM 2017…


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