Author Archives: sdavis

Intel Unveils More 10nm Details

By Dick James

On March 28, Intel held a Technology and Manufacturing Day in San Francisco, not surprisingly focusing on the work of the Technology and Manufacturing Group (TMG) within the company. This event was an exposition of the 10nm process, a new 22FFL ultra-low-power process, a quick mention of EMIB packaging, a plug for the enhanced 14nm technologies, some more marketing of Intel foundry, and all within the context of “Moore’s Law is alive and well at Intel!”

10nm-1

 

Getting straight to the 10-nm presentation, which was the fourth of the day, Kaizad Mistry unveiled some of the mysteries:

10nm-2
He put the numbers up remarkably quickly:

10nm-3

We had speculated in the last blog that self-aligned quadruple patterning (SAQP) would be used for the fins, and it would be “really ambitious” for metal definition; and Intel have surprised us by being really ambitious! Going below 40nm takes us into the realm of SAQP, or alternatively LELELE (litho-etch, litho-etch, litho-etch), adding to the complexity and cost of the process; Intel obviously considers the extra bump in density worth the cost. It also likely sets them up for the next node; take the pain now, and hopefully reduce the time to 7nm!

The gate pitch was announced at IDF as 54nm, and we now know the fin pitch is 34nm, the metal pitch is 36nm, and the cell height is 272nm. Taller fins were also mentioned, and indeed we have that, with an increase from 42 to 53nm:

10nm-4

Putting a ruler on the fins, we come up with a fin width of 5 – 15nm, and ~7nm at half height. Gate width is ~110nm, compared with the ~85nm of the previous generation. Gate length is still an unknown, but we can speculate that it will be in the 18 – 20nm range, assuming dielectric thickness of ~8nm between the gate and contacts.

Kaizad claimed a 25% performance improvement, with another 15% to come from the 10++ version in a couple of years, and corresponding power reduction to 0.55x, and 0.7x for the 10++ sub-generation.

10nm-5
Two other elements of the hyper scaling were also detailed; contact over active gate (COAG), and single dummy gate (SDG), which in total are claimed to add another 30% transistor density improvement.

COAG means moving the contact from a position away from the fins to directly over the active part of the gate:

10nm-6

We can perhaps see the concept a bit more clearly in this (somewhat fuzzy) image of 14nm transistors:

10nm-7

We can see here that if we can somehow squeeze the gate contacts in between the source/drain contacts, then we don’t need the vertical space for them, and we can shrink the cell height; the vertical distance between the gates is reduced to the gate tip/tip spacing. However, this strikes me as quite a challenge, likely requiring at least self-aligned gate contacts, and it’s no wonder that Kaizad commented that “there are a number of technology attributes and innovations that we needed to introduce to allow the contact to be placed directly above the active transistor.” This extra complexity may mean that the cell architecture could have also changed, and the routing metal may not be at the minimum pitch; the minimum metal may start at the M3 level.

For the single dummy gate, he also said that Intel “introduced unique innovations to overcome the difficulties of single dummy gate,” to ensure that the performance of centre transistors and the edge transistors are closely matched.

10nm-8

The dummy gates are shown in the plan-view image above, but what can’t be seen is that he dummy gates usually overlap the end of the fin, unlike the left-hand schematic above. Here’s a shot of 22nm PMOS gates on a fin:

10nm-9

This clearly adds to the width of the cell, but it has the advantage of matching the performance of all the transistors on the fin. If we have a single dummy gate on the STI between the fins, as in the Samsung 14nm and earlier 20nm devices, then the source/drain cavity etch and the contacts are on or near the ends of the fin. They are then subject to overlay errors, increasing variation in both the contact resistance and the source/drain epi growth.

The simplest structure to get rid of this problem would be to do without the STI between fins, making the dummy gate some sort of isolation structure, but presumably that would mean having contacts to those gates to keep them tied to the correct potential – adding more complexity to the structure and design rules. We’ll see what those “unique innovations” are when the part comes out!

In total these changes make for a shrink beyond the usual 50% to 37% of the 14nm technology:

10nm-10

Intel claims that this hyper-shrink actually brings them back on to a two-year cadence from the 45nm node, assuming high-volume production as of the second half of this year.

10nm-11

The SRAM cells are scaled by a factor of ~0.6, so that the low-voltage 1:2:1 (fins in Pull-Up:Pass-Gate:Pull-Down transistors) cell goes from ~0.059 µm2 to ~0.037 µm2, and the high-density 1:1:1 cell shrinks from ~0.050 µm2 to ~0.031 µm2. (The TSMC and GF/IBM/Samsung 7-nm cells announced at IEDM, presumably 1:1:1 cells, were 0.027 µm2.)

If we look at the transistor image, there are features in common with the 14-nm device. Comparing at the two cross-sections, it appears that the solid-source punch-stop diffusions introduced at 14-nm are present, since we can see the seal layer(s).

10nm-12

 

Looking at the gate stacks, we do not seem to have any significant change, so we now have the fifth generation of Intel’s HKMG technology, and of course it’s their third-generation finFET.

Things are not getting any easier, not the least getting the gate and contact materials into ever smaller spaces. With a smaller fin pitch the implant angle needed for doping is also shrinking; I measured it as less than 30o, compared with the 52o and 41o of the 22- and 14nm processes, but I am told that if the implant has a twist (i.e. angled with respect to the fin orientation), then it is till feasible to get implants into the right location.

Taller fins with higher aspect ratios will have their own mechanical challenges, implying tighter stress control to avoid fin bending and distortion, which was quite noticeable in some samples of the 14nm product.

We could go on detailing more problems, but suffice it to say that I don’t have much sympathy with some of the media criticism that I see of the slow-down in process generations. It wasn’t easy in the days of Grove, Kilby, and Moore, given the technologies of the time, and now that we are counting atoms it certainly isn’t any easier – don’t forget that a 7nm fin is actually less than 25 atoms wide!

Intel’s 10nm Enigma

By Dick James

I’ve been looking back at the talk given by Mark Bohr and Zane Ball (Building Winning Products with Intel® Advanced Technologies and Custom Foundry Platforms) at the Intel Developer Forum (IDF) in August last year, and I’m a bit puzzled.

Mark Bohr presenting at the 2016 IDF in San Francisco (Source: Intel)

Mark Bohr presenting at the 2016 IDF in San Francisco (Source: Intel)

Mark announced the gate pitch as 54 nm, which I make as 0.77 x 70 nm (the 14-nm gate pitch):

Gate pitch

And he also said that their measure of scaling is gate pitch x cell height:

Cell size

and then he said that new design rules give even better scaling:

Cell size 2

“Our trend in reducing logic cell area has been about 0.46x per generation, a little bit faster than the typical Moore’s Law of 0.5x.

On our last two generations, 14 nm and now on 10 nm, we’re actually scaling our logic cell area a little bit faster than what that simple metric suggests; there are some other tricks that we’re doing on 10 nm that is providing even faster than normal logic cell area scaling, so although 0.46x was the long-term trend over the past four generations, it’s actually a bit faster on our 14 and now again on our 10-nm technology.”

If you look at the numbers in the revised graph, then we appear to have a scaling factor of ~0.37 per generation, which is indeed quite impressive!

The cell height can also be measured by the number of metal tracks that are needed for routing for the cell; in recent nodes we have gone from 12-track (12T), to 9T, to ~7.5T in the latest 14- and 16-nm processes. So we can also describe cell height as the number of metal pitches (MPP) in a cell.

That leads me to the enigma – if you take the 10-nm number from the above graph, ~11,000 nm2, and divide the 54-nm gate pitch into it to get the cell height, and then divide that by the minimum SADP (self-aligned double patterning) metal pitch of ~40 nm to get the number of tracks, then you get a five-track cell, which seems really ambitious for a one-generation shrink.

If you go the other way and plug in 54 nm and a six-track cell, then the MPP comes out at 34 nm, which presumably means SAQP (self-aligned quadruple patterning), which again sounds really ambitious.

The 5T cell is more in keeping with “design rule enhancements” but if that is the case, that also requires a reduction in the number of fins per transistor, which implies taller fins or other tweaks to maintain transistor performance; or SAQP for fin definition, to allow increased fin density. Given that the 14-nm fin pitch was ~42 nm, already close to the SADP limit, the latter may be a real possibility (a 76% linear shrink would be ~32 nm).

If they’ve done any of these, I guess it could account for the increased time between generations!

Mark also broke with the current convention of showing performance plots with the dreaded “arbitrary units”, later in the talk he showed the four transistor options available in their 10-nm process:

Transistor options

According to Mark, the four options will use the same 54nm gate pitch. NMOS drive currents are still higher than PMOS, which to me suggests two things – there is a seventh-generation strain mechanism at work for NMOS, and it seems unlikely that we have a different channel material such as SiGe in the PMOS devices.

In keeping with their foundry ambitions, there will be three evolutions of the 10-nm process, with the initial launch of 10, then 10+ and 10++, as well as a SoC version of the process with high-voltage and analog elements, and three interconnect stacks. In any case, these numbers do support the Intel claim that their process is a true shrink from 14 nm, not just an improved 14-nm process.

The increased shrink allows Intel to stay ahead of the cost curve, so that we still have improved PPAC (performance/power/area/cost) numbers.

Transistor cost

We will see if any more information comes from the quarterly call this week, or at the Investor Meeting next month, but in the meantime, we have our mystery – do we have a five-track cell, or am I missing something?

IEDM 2016 – Setting the Stage for 7/5 nm

By Dick James

At IEDM last month, there was much ado about the adjacent 7-nm late-news papers from TSMC and the GLOBALFOUNDRIES/IBM/Samsung group consortium from the Albany Nanotechnology Center, and with less ado, Samsung gave a 5-nm presentation later in the conference. Here we discuss all three talks, and try and make some comparisons.

TSMC 7 nm

In paper 2.6 [1], TSMC announced the “world’s first 7nm CMOS platform technology for mobile system-on-a-chip (SoC) applications, featuring FinFET transistors”. They claimed the world’s smallest-ever SRAM cell at 0.27 µm2, and 3x the gate density of the 16-nm (16 FF+) process, together with a 35 – 40% speed gain or over 65% power reduction. In addition, the process uses 193 nm immersion lithography, dual raised source/drain epi, a novel contact technique, and a 12-layer copper/low-k interconnect stack.

The fourth-generation fin profile and width are “carefully optimized” for the fifth-generation HKMG gate-last, dual gate oxide process, with an effective gate length (leff) centered around 16.5 nm. Sub-threshold swing has been pushed down to ~65mV/decade, and DIBL is ~40 mV/V.

TSMC SRAM IEDM

Four Vt options are available in the TSMC 7-nm technology [1]

There are four device Vt options with a range of ~200 mV.

The contacted poly pitch (CPP) is not stated (Scotten Jones speculates that it is 54 nm, the same as Intel’s 10-nm process), enabled by a novel contact process, and we also have “novel strain engineering and new process knobs” which boost mobility and reduce parasitic resistance to give increased drive current (at least in arbitrary units).

The 1x metal pitch is 40 nm for M0 to M4, and M5 – M9 are 1.9x (76 nm). The paper states that “single patterning is adopted for metal layers with 2X minimum metal pitch and above” – which make me wonder if they’ve managed to push single patterning to the 76-nm pitch, or whether they are going with double patterning for the first nine levels.

An earlier SRAM paper was given in June at the VLSI meeting [2], as a sub-0.03 µm2 bitcell, aimed at a “beyond 10-nm node”, so likely the same SRAM. It also has an leff centered on ~16.5 nm, and claims similar performance figures. Some details of the inter-well spacing are also included [1]:

TSMC SRAM VLSI

Which allows us to speculate about device sizings, at least in the SRAM cell itself. Typically, a 6-transistor (6T) SRAM unit cell is 2 x CPP high, so if we take the guesstimate of 54 nm for CPP, the 0.27 µm2 cell should have a height of 108 nm. Dividing that into 27,000 nm2, we get a cell width of 250 nm. The 16FF cell was 0.70 µm2 [3], 2.6 x the area of the 7-nm cell, confirming the claim of a 2.6 x array density increase in the paper.

I don’t have a plan-view image of the TSMC 16-nm cell, which I assume is a 1:1:1 PU:PG:PD cell (i.e. one fin for each of the pull-up/pass gate/pull-down transistors), but Intel kindly provided one of their 14-nm cell in a JSSC paper [4]:

TEM image of Intel 14-nm SRAM cell [4]

TEM image of Intel 14-nm SRAM cell [4]

The Intel 14-nm cell size is 140 x 360 nm, to give a cell size of ~0.050 µm2, considerably smaller than the 16FF cell; we can see that each transistor uses one fin, and there are four fins in the cell. In this case the fin pitch is ~80 nm, instead of the nominal 42 nm, but we have to allow space between the fins and the edge of the N-well that the PMOS pull-up transistors sit in. Theoretically the two pull-up transistor fins could use the minimum pitch, but Intel have chosen not to do that here.

Applying these considerations to TSMC’s cell, if we use the maximum fin-well edge spacing of 23 nm shown above, plus (say) 8 nm for the fin width, then we get a PU – PD/PG spacing of 2 x 23 = 46, + 8 = 54 nm; if we assume a SADP (self-aligned dual patterning) minimum fin pitch of 40 nm between the PU transistors, then we get a total of 148 nm for the center of fin 1 – fin 4, which leaves us 52 nm at each end for the PD/PG – PG contact spacing. If the PU/PU pitch is also 54 nm, that only leaves 45 nm at the end of the cell, which is pushing the limits for double-patterned contact spacing. Which gives us something like this – just guessing!

Speculative layout of TSMC 7-nm SRAM bitcell

Speculative layout of TSMC 7-nm SRAM bitcell

GLOBALFOUNDRIES/IBM/Samsung 7 nm

The other 7-nm paper [5] from Albany was clearly a research paper, but illuminating in that it shows other possible directions, not the least being the use of EUV lithography, SiGe channels for PMOS, and stress applied to the channels using a strain-relaxed buffer (SRB) substrate.

The application of a SRB substrate to generate channel stress takes me back 15 – 20 years, to the late 90’s and the turn of the millennium, when a lot of work was published on the topic by Stanford, MIT, and IBM. If a silicon epitaxial layer is grown on a SiGe substrate, then the lattice mismatch creates biaxial tensile stress in the layer, and the greater the Ge content, the greater the stress. The earliest reports I can find date back to 1992/4/5 [6, 7, 8,], but the effect is nicely summarized in this plot from IEDM 2003 [9]:

Mobility enhancement vs. strain and Ge % in strained Si/relaxed SiGe MOSFETs [9].

Mobility enhancement vs. strain and Ge % in strained Si/relaxed SiGe MOSFETs [9].

As we can see, low Ge concentration gives a large increase in electron mobility, but a high Ge content is required to enhance hole mobility.

In this paper, we have the following structure:

Schematic (center) of dual-stressed channel materials on the SRB with a super-steep retrograde well (SSRW), along with dark-field TEM images of (a) the tensile-strained silicon fin and (b) the compressively-strained SiGe fin on a common SRB [5]

Schematic (center) of dual-stressed channel materials on the SRB with a super-steep retrograde well (SSRW), along with dark-field TEM images of (a) the tensile-strained silicon fin and (b) the compressively-strained SiGe fin on a common SRB [5]

This gets around the weak PMOS improvement in silicon from the SRB by using 25% Ge in the SRB and growing a 50% Ge fin; if silicon is tensile-stressed, then a layer with more Ge than the SRB will be compressively stressed; and as we know, compressive stress is a big lever for PMOS performance. The authors claim that this combination gives ~1.6 GPa enhancement stress in both NMOS and PMOS devices. SiGe also has a higher hole mobility, compounding the performance gain.

As I remember it, SRB stress never made it into production, likely for two reasons – it was difficult to get rid of the dislocations formed in the SRB, and they propagated through into the sSi; and more production-friendly sources of uniaxial stress could be supplied by tensile nitride and embedded SiGe source/drains.

Now that we are in the finFET era, and twenty years on, we have the advantage of better process control, (so likely lower defect density), and any defects that are formed cannot propagate up the fin because of its narrow aspect ratio. In addition, fins formed in the correct orientation on a SRB use only one axis of the biaxial stress, giving the uniaxial stress that we are used to; so maybe this technique can become the stress mechanism for the 7/5 nm nodes.

Biaxial stressed layer becomes uniaxially-stressed finFET [10]

Biaxial stressed layer becomes uniaxially-stressed finFET [10]

If I read the paper correctly, the SSRW is grown epitaxially as part of the SRB (“An epi based SSRW technique is utilized to improve sub-fin isolation” [5]), before the strained silicon (sSi) epi is grown; the sSi is then etched back and the 50% SiGe layer is formed and (presumably) polished back to separate the sSi and SiGe regions before fin etch [11].

Self-aligned quadruple patterning (SAQP) was used for the fins (my notes say the fin pitch was 27 nm), and SADP for the gates with a CPP of 44/48 nm. EUV was reserved for the middle-of-line (MOL) and lower metal levels, with a minimum metal pitch of 36 nm.

(a)Schematic flow for SAQP fin patterning (b) top-down SEM of fins before cut/block mask [5] Top-down SEMs of (a) BEOL M1 lines with 36nm pitch, and typical MOL trenches with (c) 45°, (d) 90° cross-couples, (24nm trench width), all patterned by EUV lithography [5]

(a) Schematic flow for SAQP fin patterning (b) top-down SEM of fins before cut/block mask [5]
Top-down SEMs of (a) BEOL M1 lines with 36nm pitch, and typical MOL trenches with (c) 45°, (d) 90° cross-couples, (24nm trench width), all patterned by EUV lithography [5]

The EUV process was presented at last year’s IITC/AMC conference [12]; a metal hard mask was used to pattern lines and self-aligned vias into an ultra-low-k dielectric (k~2.45), and a TaN/Ru liner stack was filled conventionally with a CVD Cu seed and plating. A Co cap and SiCN/SiNO layer sealed the interconnect, giving acceptable TDDB (time-dependent dielectric breakdown) and electro-migration results.

M1 – M3 stack in test die used in [12]

M1 – M3 stack in test die used in [12]

Cross section and elemental mapping of M1 Cu lines with TaN/Ru barrier and selective Co cap [12]

Cross section and elemental mapping of M1 Cu lines with TaN/Ru barrier and selective Co cap [12]

Contacts are self-aligned, with the use of a M0 level, CA/CB contacts, and a sub-contact (TS) for source/drains. The CA/CB/M0 metallization is dual-damascene cobalt, lowering line resistance, while the TS sub-contacts appear to be tungsten. Before the TS contacts are filled, Si:P and SiGe:B epi is grown in the contact trenches, and then implanted and annealed, to give improved contact resistance.

Middle-of-line architecture (left), and dark-field TEM of M0/CA/TS stack [5]

Middle-of-line architecture (left), and dark-field TEM of M0/CA/TS stack [5]

The gate profile was modified by etching back the high-k layer before depositing the work-function metal (WFM), which helps isolate the high-k from the self-aligned contact process reactants, and improves control of the WFM recess before metal fill and dielectric deposition.

Cross-section TEM of <17 nm gate showing etch-backs of high-k and WFM [5]

As you can see from the above, there was quite a bit of detail in this presentation, which can be summarized in the process sequence shown [5]:

IBM flow

Strangely, despite the tighter pitches when compared with the TSMC SRAM bitcell, the size is the same, ~0.27 µm2, though we don’t know if this is a 1:1:1 cell or not – if (say) a 1:2:1 configuration is used, that would add at least ~0.052 µm2 to the cell size, assuming the 48 nm CPP. (The paper does not state bitcell size, but in the Q & A’s, we were told that it was 50% of the 10-nm bitcell, which was quoted at ~0.53 µm2.) The Q & A’s also mentioned that there were three flavours of Vt, and high-Vt I/O transistors were not studied, reinforcing the research nature of the paper.

Samsung 5 nm

Later in the conference (paper 28.1), Samsung presented a “co-integration scheme for 5nm logic” [13] which clearly drew on the 7-nm work from Albany detailed above, and illuminating some more development problems that that must have been seen in Albany.

A SRB substrate is used with a SiGe fin for PMOS, and a common interlayer, high-k, and work-function materials. The SiGe fin, combined with e-SiGe source/drains, gives an estimated 1 GPa compressive stress, and the SRB applies similar tensile stress to the NMOS channel. As with the Albany process, the Ge concentration increases as we go from SRB to fin to e-SiGe source/drains.

Schematic of Samsung 5-nm CMOS design concept [13]

Schematic of Samsung 5-nm CMOS design concept [13]

Defect density from the SRB was definitely a concern, and was reduced to 5e4/cm2, and then demonstrated by SRAM that leakage levels are comparable with those of a reference SRAM structure on bulk Si. My notes say that a thicker SRB was used, but no actual thicknesses were mentioned.

SiGe SRB TDD evolution with lowest TDD of 5e4/cm2 (left), 128M finFET SRAM with TDD 2.3e5 /cm2 (right) shows comparable yield and leakage with reference SRAM [13]

SiGe SRB TDD evolution with lowest TDD of 5e4/cm2 (left), 128M finFET SRAM with TDD 2.3e5 /cm2 (right) shows comparable yield and leakage with reference SRAM [13]

Another problem was migration of the Ge to the surface of the SiGe fin (shifting Vt and degrading interface state density), because of later thermal processing, as shown in this LEAP (laser enhanced atom probe) image:

Ge (blue) in SiGe fin, showing higher Ge content at the surface [13]

Ge (blue) in SiGe fin, showing higher Ge content at the surface [13]

Careful optimization of the thermal sequencing reduced this to about a 4% variation. Since the STI penetrates into the buffer layer, and we have a SiGe fin, a new STI formation process had to be developed, to reduce any side-effects from oxidation.

More details were given of the stress development; the presenter showed that the strain was uniaxially transferred to the fin, and also that the source/drain recess etch relaxed the channel stress – in the PMOS device the e-SiGe epi restored the stress, but for NMOS a non-recessed S/D was used.

Geographic phase analysis (GPA) shows uniaxial (along fin) tensile strain induced by SRB, and strain fully relaxed perpendicular to fin (a). Strain profile along fin depth shows uniaxial strain along fin but almost fully relaxed strain across fin (b) [13]

Geographic phase analysis (GPA) shows uniaxial (along fin) tensile strain induced by SRB, and strain fully relaxed perpendicular to fin (a). Strain profile along fin depth shows uniaxial strain along fin but almost fully relaxed strain across fin (b) [13]

When it comes to the electrical results, long- and short-channel plots were shown, but with no numbers for either device size or measurements, so we have to trust that they actually fit 5-nm node dimensions, or at least are for smaller pitches than the 7-nm papers detailed. However, as an integration scheme it is interesting, as gives us some clues as to what we might see from Samsung and GLOBALFOUNDRIES as we go from 10 – 7 – 5 nm.

Given the lack of detail in TSMC’s presentation, we don’t know what their novel contact and strain engineering and process knobs are – could they be contact epi and SRB strain? I guess we’ll see in a couple of years or so.

N/PFET channel average stress evolution during processing – the relative strain clearly shows relaxation from the S/D recess process. After recess optimization, relaxation was minimized for the NFET (but non-recessed process chosen), and recovered with eSiGe process [13]

N/PFET channel average stress evolution during processing – the relative strain clearly shows relaxation from the S/D recess process. After recess optimization, relaxation was minimized for the NFET (but non-recessed process chosen), and recovered with eSiGe process [13]

References

  • S-Y Wu, et al., “A 7 nm CMOS Platform Technology Featuring 4th Generation FinFET Transistors with a 0.027 um2 High Density 6-T SRAM cell for Mobile SoC Applications”, IEDM 2016, pp. 43 – 46
  • S-Y Wu, et al., “Demonstration of a sub-0.03 um2 High Density 6-T SRAM with Scaled Bulk FinFETs for Mobile SOC Applications Beyond 10nm Node”, VLSI 2016, pp 92 – 93
  • S-Y Wu, et al., “An Enhanced 16nm CMOS Technology Featuring 2nd Generation FinFET Transistors and Advanced Cu/low-k Interconnect for Low Power and High Performance Applications”, IEDM 2014, pp. 48 – 51
  • Karl, et al., “A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry”, IEEE JSSC, VOL. 51, NO. 1, (Jan 2016), pp. 222 – 228
  • Xie et al., “A 7nm FinFET Technology Featuring EUV Patterning and Dual Strained High Mobility Channels”, IEDM2016, pp. 47 – 50
  • Welser et al., “NMOS and PMOS Transistors Fabricated in Strained Silicon-Relaxed Silicon-Germanium Structures”, IEDM 1992, pp. 1000 – 1002
  • Welser et al., “Strain Dependence of the Performance Enhancement in Strained-Si n-MOSFETs”, IEDM 1994, pp. 373 – 376
  • Rim, et al., “Enhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETs” IEDM 1995, pp. 517 – 520
  • Rim, et al., “Fabrication and Mobility Characteristics of Ultra-thin Strained Si Directly on Insulator (SSDOI) MOSFETs”, IEDM 2003
  • IEDM 2016 Short Course, “Technology Options at the 5 Nanometer Node”, session 3, N. Collaert, “Novel channel materials for high-performance and low-power CMOS”, sl. 17
  • Guo et al., “FINFET Technology Featuring High Mobility SiGe Channel for 10nm and Beyond”, VLSI 2016, pp. 14 – 15
  • Standaert, et. al., “BEOL Process Integration for the 7 nm Technology Node”, IITC/AMC, 2016, pp. 2 – 4
  • D, Bae et al., “A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond”, IEDM 2016, pp. 683 – 686

IEDM 2016 Next Week! (Part 2)

By Dick James, Senior Technology Analyst, Chipworks

Read Part 1 here.

Now for the second part of the preview, starting with the Tuesday afternoon sessions:

Session 17: Process and Manufacturing Technology — Silicon Based Advanced CMOS

Here we look ahead a little, considering how silicon will evolve rather than using other higher-mobility materials. First up is a joint IBM/GF report of air spacers in 10nm finFET structures (17.1), between the gate and the contacts, to reduce the parasitic capacitance.

Schematic of partial air spacers (left), and TEM cross-section of finFET gates, showing spacers between gates and contacts (17.1)

Schematic of partial air spacers (left), and TEM cross-section of finFET gates, showing spacers between gates and contacts (17.1)

IBM/GF also study (17.2) the use of laser-induced liquid- or solid-phase epitaxy in contact trenches, to form semi-metallic, semiconductor-dopant (Si:P and Ge: group III metals) metastable alloys to reduce contact resistance.

17.3 also considers contact resistance, this time looking at Ni(Pt) silicide on fin-on-insulator (FOI) finFETs. IBM/GF are up again in 17.4, discussing low Ge-content SiGe finFETs; imec and Applied Materials are collaborating in the usage of high-temperature ion implantation in bulk finFET technology (17.5); next we look at vertically-stacked horizontal nanowires with replacement metal gates (RMG), inner spacers, and SiGe source/drain stress for p-FETs (17.6); and finally we have an FD-SOI paper, discussing a dual-isolation process (STI and local oxidation) to maximize both SiGe-channel stress and back-biasing performance(17.7). 

Session 18: Sensors, MEMS, and BioMEMS Enhanced Sensing, Heterogeneous Integration and Wearables

We start this session with a report (18.1) on using pre-bias to improve the sensitivity of a silicon FET gas detector which has ZnO as a sensing layer. Then Fujitsu describes a graphene-based gas sensor capable of detecting 7 ppb of nitric oxide (18.2), and in 18.3 laser-patterned graphene is used for strain sensing.

Graphene shows up again as a transparent epidermal sensor in 18.4, measuring skin temperature, hydration and electrophysiological signals (ECG, EEG, EMG). Prof. Shuji Tanaka of Tohoku University gives an invited talk on “Heterogeneously-Integrated Microdevices” in 18.5, then flexible (i.e. thin) bulk silicon is used for the system-level monolithic integration of multiple sensor types using CMOS processing, including a wearable version (18.6).

The session finishes (18.7) with an invited review by Raji Baskaran of Intel, on “Sensors and Haptics Technologies for User Interface Design in Wearables”. 

Session 19: Nano Device Technology — Tunnel and Nanowire FETs

The first paper combines both themes of the session – we have a vertical nanowire InAs/GaAsSb/GaSb tunnel FET (19.1) with a record high on-current of 10.6μA/μm.

Schematic of InAs/GaAsSb/GaSb TFET (left), and a colorized SEM image of a nanowire with W gate metal applied (19.1)

Schematic of InAs/GaAsSb/GaSb TFET (left), and a colorized SEM image of a nanowire with W gate metal applied (19.1)

19.2 is an invited review of a “Two-dimensional Heterojunction Interlayer Tunnel FET (Thin-TFET): From Theory to Applications” by Mingda Li from Cornell. The ThinFET was formed from WSe2/SnSe2 stacked heterostructures, which intrinsically has a smaller gate-drain capacitance due to its vertical stack.

Next we have the first hybrid Phase-Change-Tunnel FET (PC-TFET) device (19.3). Experimental digital and analog benchmarking of the new device was performed, and it was compared with Tunnel FETs and CMOS; it was also included into a neuromorphic computing cell, taking advantage of the phase-change mechanism.

Isoelectronic trap technology (IET) is used to improve the performance of silicon-based TFETs in 19.4, and Shinichi Takagi of U. Tokyo gives an invited review (19.5) of “Tunneling MOSFET Technologies using III-V/Ge Materials”.

The next paper details InGaAs/GaAs and Ge/GeSn p-TFETs on GaAsSb and GeSn substrates (19.6), and the last paper harks back to nanowires, this time vertical silicon GAA-NW transistors with a dual work-function, high-k last RMG process (19.7).

Session 20: Power Devices — Focus Session: System-level Impact of Power Devices

This session focuses on the use of GaN and SiC power devices and how they have expanded the spectrum of applications to very high voltages, temperatures and power levels, compared to existing silicon-based devices.

It comprises a sequence of invited talks:

  • Wide Bandgap (WBG) Power Devices and Their Impacts On Power Delivery Systems,” by Alex Huang, North Carolina State University
  • Si, SiC and GaN Power Devices: An Unbiased View on Key Performance Indicators,” by G. Deboy et al, Infineon/ETH-Zurich
  • System-Level Impact of GaN Power Devices in Server Architectures,” by A. Lidow et al, Efficient Power Conversion Corp.
  • GaN-based Semiconductor Devices for Future Power Switching Systems,” by H. Ishida et at, Panasonic
  • Application Reliability Validation of GaN Power Devices,” by S. Bahl et al, Texas Instruments
  • Horizon Beyond Ideal Power Devices,” by H. Ohashi, NPERC-J (Japan’s New-Generation Power Electronics & System Research Consortium)

 Session 21: Characterization, Reliability and Yield — Reliability and Characterization of Memory Devices, Contacts and Interfaces

This session starts with a reliability study of a 128 Mb GaSbGe PCM device (21.1), followed by an examination of the effect of filament shape on Cu/Al2O3 CBRAMs (21.2).

21.3 investigates the microsecond transient thermal behavior of HfOx-based RRAMs, and 21.4 identifies the switching/failure mechanisms in non-filamentary RRAM.

Back in September GLOBALFOUNDRIES and Everspin announced production of Everspin’s 256 Mb DDR3 perpendicular magnetic tunnel junction (pMTJ) product, and availability of the embedded version of the technology on GF’s 22FDX platform. Jon Slaughter of Everspin is giving an invited talk (21.5) “Technology for Reliable Spin-Torque MRAM Products”, which will include a review of the performance of the 256 Mb, DDR3 ST-MRAM chip.

In 21.6 we have an endurance study of perpendicular spin-transfer torque (p-STT) memory, and 21.7 describes Schottky contacts between silicon and graphene, to finish the session. 

Session 22: Optoelectronics, Displays, and Imagers — Optoelectronic Integration

We start with GeSn thin-film transistors (TFTs) formed on a quartz substrate, which have high carrier mobility and luminescence (22.1). The second paper utilizes the optical properties of SOI wafers to couple an InGaAsP laser to a pair of distributed Bragg reflectors (DBRs) and a grating coupler diffracting the light to an optical fiber (22.2).

Schematic of a heterogeneous hybrid III-V/Si DBR laser cavity with the gain zone, two DBRs and a grating coupler at one side diffracting the light to an optical fiber (22.2)

Schematic of a heterogeneous hybrid III-V/Si DBR laser cavity with the gain zone, two DBRs and a grating coupler at one side diffracting the light to an optical fiber (22.2)

22.3 is an invited presentation by Dan Buca of Forschungszentrum Julich, “GeSn Lasers for CMOS Integration”, followed by a description of a high-gain optical amplifier, monolithically integrated with an InGaN-based laser diode (22.4).

A germanium-on-silicon Zener emitter is detailed in 22.5, and NXP and A*STAR come up with a surprising method of optically sensing the states of flash memory in the last paper (22.6); they demonstrate it with the on-chip integration of an optical micro-ring resonator and a memory array, and claim 1200× sensing speed improvement.

That is numerically the last paper of the afternoon, if not chronologically – the sessions with seven papers finish at ~5.15 pm.

In the evening at 8 pm we have the panel sessions in the Continental Ballrooms:

  • How Will the Semiconductor Industry Change to Enable 50 Billion Connected Devices? Moderator: Prof. Aaron Thean, University of Singapore
  • Challenges and Opportunities for Neuromorphic and Machine Learning, Moderator: Marc Duranton, Sr. Member of the Embedded Computing Lab, CEA

But, if you have the stamina after a day-full of technology, Applied Materials, Coventor and Synopsys are holding seminar/receptions between 5 and 8 pm. The Applied Materials event is at the Parc 55 hotel just around the corner from the Hilton, on “Rethinking Scaling: New Paradigms, New Approaches”, and Coventor is looking at the back-end “BEOL Barricades: Navigating Future Semiconductor Yield, Reliability and Cost Challenges”, in the Union Square rooms on the 4th floor of the Hilton. The Synopsys reception is around the corner at the Serrano Hotel from 6 – 8 pm.

Wednesday

Session 25: Process and Manufacturing Technology — Beyond Conventional CMOS

25.1 looks at the contribution to source/drain resistance made by interfaces such as the p-SiGe/p-Si interface, and also studies the n-Si/n-Ge, n-InAs/n-Si and n-InAs/n-Ge interfaces.

The second paper examines the effects of doping HfO2 with different ions, both cations and anions, in order to influence and predict ferroelectric properties; and demonstrates an N-doped dielectric layer in a ferroelectric FET (25.2).

Next up is a description of an AgTe/TiO2-based threshold switching (TS) device that can be integrated with a conventional BEOL (25.3). When switched on, a conductive silver filament forms, and when switched off, the filament dissolves and conduction stops. A TiN liner is put between the AgTe and the TiO2 to prevent silver diffusing into the TiO2 during BEOL processing; a steep subthreshold slope of less than 5 mV/decade is claimed.

Schematic and TEM image of the integrated TS transistor (25.3)

Schematic and TEM image of the integrated TS transistor (25.3)

We live up to the theme of “Beyond Conventional CMOS” in 25.4; here we have InGaAs-on-insulator MOSFETs, fabricated by direct wafer bonding (DWB)and epitaxial lift-off techniques, aimed at monolithic 3D integration; and in addition, the InP donor wafer can be re-used.

We stay with wafer bonding in 25.5, but in the photonics realm; an InGaAsP/Si hybrid MOS-based phase shifter formed on a Si photonics platform by using DWB is described.

The last talk of the session is an invited one, by Janos Veres of Xerox PARC; “Additive Manufacturing for Electronics “Beyond Moore””. The ability of additive manufacturing and 3D to change the paradigm of electronics production will be discussed. 

Session 26: Sensors, MEMS, and BioMEMS — N/MEMS for Physical, Chemical, and Bio-sensing

A solid-state pH and chloride sensor is formed from iridium oxide (IrOx) and silver chloride (AgCl) electrodes fabricated on a Si substrate in 26.1, with a microfluidic reference electrode incorporated. 26.2 describes the use of a spin-transfer torque operated magnetic tunnel junction (STT-MTJ) to make a thermal sensor more than 0 times faster than a traditional CMOS thermal sensor.

Next Chae Ahn from Stanford gives an invited talk (26.3) on the challenges of encapsulating MEMS timing reference devices, with particular reference to those produced by SiTime Inc; and the influence of the thickness of a tribo-dielectric layer on the performance of a tribo-electric energy harvester is described in 26.4.

In 26.5 we look at a brain probe which uses neuron-sized LEDs to stimulate the neuronal proteins with light instead of electrically. Micro-LEDs and electrodes are integrated on thin silicon probes formed by micro-machining to give a four-probe opto-electrode which can be inserted into the target area of the brain.

The four shanks of an optoelectrode with its tips are shown (26.5), with the LEDs illuminating. The inset (left) shows a SEM view of a tip.

The four shanks of an optoelectrode with its tips are shown (26.5), with the LEDs illuminating. The inset (left) shows a SEM view of a tip.

The effect of Lamb waves (sound waves confined to a thin layer) on the two-dimensional electron gas (2DEG) in an AlGaN/GaN heterostructure are studied in 26.6, generating an acousto-electrical effect that results in DC current flow between contacts on the acoustic layer.

In 26.7 a micro-oven is used to control a CMOS-MEMS oscillator, with a built-in temperature detector for self-test and resonator temperature monitoring; and in the last talk (26.8), self-assembled perfluorodecyl-triethoxysilane (PFDTES) is used as an anti-stiction coating on the contacting parts of a nano-electro-mechanical relay. 

Session 27: Memory Technology — MRAM

Hynix and Toshiba kick off the session with a joint paper (27.1) on a 4-Gb perpendicular SST-MRAM (spin-transfer-torque magnetic random access memory) with a 9F2 cell area. The vertical stack and a plan-view SEM image of the MTJ array are shown below, clearly using some of the techniques used in DRAMs, such as buried wordlines.

27.1

Just eyeballing the scale bar on the SEM image, it looks like the MTJ cell diameter is ~50 nm, which compares with ~60 nm in a 20-nm DRAM.

This is followed by a Samsung exposition (27.2) of an 8-Mb STT-MRAM embedded into the BEOL of their 28-nm logic process, again using a perpendicular MTJ (pMTJ). Third up (27.3) is a study of data extraction methods for perpendicular SST-MRAM, to evaluate retention as cell size decreases from 250 nm to 50 nm in diameter.

Qualcomm and Applied Materials shrink the pMTJ cell size even further in 27.4, down to 25 nm, studying the properties in 1-Gb arrays. 27.5 is an examination of a voltage-torque MTJ MRAM; and in the last paper (27.6) Toshiba describes another voltage-controlled MTJ, with volts used to select bits, and spin-torque to write.

Session 28: Circuit and Device Interaction — Technology Elements for 5nm Logic Platform and Advanced Automotive/IoT Applications

Samsung manages to integrate strained Si-channel NMOS and SiGe-channel PMOS finFETs in 28.1, using a buried strain-relaxed SiGe buffer layer to create tensile-strained NMOS and compressively-strained PMOS devices. The gate stack uses a common interfacial layer, high-k, and metal gate, without dual-work-function metals, and a simplified multi-Vt module.

Imec (28.2) discusses a 5-track standard cell (Intel’s 14-nm uses 7.5-T cells) optimized for finFETs and horizontal nanowires, using single-fin design and air-gap spacers. Stanford and ARM analyse a 32-bit processor core designed with 5-nm design rules (28.3), looking at transistor and interconnect technologies.

In the next paper (28.4), a new method of near-threshold-voltage (NTV) design optimization for FinFETs is developed, and demonstrated based on silicon data using Vdds of 199 and 145 mV.

In 28.5 Xilinx looks at high-speed analog circuits, and presents an optimized MOS varactor design and finFET model; both were validated in a 16-nm finFET process in a high-speed transceiver design.

The final talk is an invited review of “Embedded Flash Technology for Automotive Applications”, by T (Tadashi?) Yamauchi from Renesas, including the integration of their split-gate MONOS eFlash into a 28-nm HKMG process.

Session 29: Compound Semiconductor and High Speed Devices — Ultra-High Speed Electronics

This session is a special focus session, again consisting of invited papers on TeraHertz technology and applications:

  • 29.1InP HEMT Integrated Circuits Operating Above 1,000 GHz,” by W.R. Deal et al, Northrop Grumman
  • 29.2A 130 nm InP HBT Integrated Circuit Technology for THz Electronics,” by M. Urteaga et al, Teledyne Scientific Co./SungKyunKwan University
  • 29.3Resonant-Tunneling-Diode Terahertz Oscillators and Applications,” by M. Asada and S. Suzuki, Tokyo Institute of Technology
  • 29.4Physics of Ultrahigh Speed Electronic Devices,” by M. Shur, Rensselaer Polytechnic Institute
  • 29.5InP/GaAsSb DHBTs for THz Applications and Improved Extraction of their Cutoff Frequencies,” by C.R. Bolognesi et al, ETH-Zurich
  • 29.6On-Chip Terahertz Electronics: From Device-Electromagnetic Integration to Energy-Efficient, Large-Scale Microsystems,” by R. Han et al, MIT/Office of Naval Research/Cornell University/University of Michigan/STMicroelectronics/University of Texas at Dallas/Naval Research Lab
  • 29.7Active Terahertz Metasurface Devices,” by H.T. Chen, Los Alamos National Laboratory
  • 29.8Devices and Circuits in CMOS for THz Applications,” by Z. Ahmad et al, University of Texas at Dallas/NXP Semiconductors/MIT/SeoulTech/Texas Instruments/MediaTek/IDT/Wright State University /UT Southwestern Medical Center/Ohio State University/ UConn Health

Session 30: Modeling and Simulation — Steep Slope Devices and Nanowires

The first paper is a TSMC study of III-V ‘broken gap’ nanowire TFETs (30.1), claiming a 58x gain increase over a Si MOSFET; followed by simulations of TFETs at Vdds of 0.08 – 0.18V (30.2).

Then we have more TFET analyses, this time of the band-tails in 2D devices (30.3), and resonant tunnelling characteristics of inter-layer TFETs with multiple tunnel barrier layers (30.4).

30.5 demonstrates models of ferroelectric negative capacitance finFETS; 30.6 examines the performance of ultra-thin body III-V finFETS and nanowires with 15 and 10.4 nm gate lengths, confirming that GAA-NWs is the only viable architecture below 10.4 nm; and the final paper is a look at vertically-stacked NW-FETs for sub-10 nm nodes (30.7).

Session 31: Characterization, Reliability and Yield — Reliability Modeling and Characterization of Dielectrics and Interfaces

In 31.1 IBM Research studies the electronic defect states at the interface between a compress SiGe channel and the interlayer dielectric of p-FETs. Samsung also looks at SiGe p-FETs (31.2), assessing the effects of acceptor traps on negative-bias temperature instability (NBTI), and coming to the conclusion that they can lower the oxide electric field and improve the NBTI performance.

Next up is a characterization of Ge p- and n-MOSFETs with an Al2O3/GeOx/Ge gate stack (31.3), followed by the presentation of a new model for looking at NBTI and PBTI (31.4). SMIC and Peking U. review the gate dielectric reliability of TFETs in 31.5, and IBM Research is back (31.6) with a model for gate oxide progressive breakdown in n- and p-FETs

We switch topics to the back-end in an investigation by TSMC (31.7) of AC TDDB (time-dependent dielectric breakdown) in BEOL extreme low-k (ELK) dielectric in (presumably) their 10nm technology.

The final talk is a presentation on the use of self-healing in gate electrodes in silicon GAA-NW FETs (31.8), aiming at electronics for deep space missions.

Session 32: Optoelectronics, Displays, and Imagers — Thin Film Transistors for Imaging and Displays

We start the session with a demonstration of an active artificial iris (32.1) built on a contact lens, and formed solely of thin-film components. It comprises an organic thin-film photovoltaic mini-module as a power supply/integrated illumination sensor; a flexible thin-film a-IGZO circuit as a driver chip; and a liquid crystal display which acts as the iris. Such a device can help with iris deficiencies that can bring great discomfort and extreme photosensitivity for sufferers.

A “smart” contact lens system, comprising an integrated display, energy harvesting components, communication antenna, sensors and more (32.1).

A “smart” contact lens system, comprising an integrated display, energy harvesting components, communication antenna, sensors and more (32.1).

In 32.2 an elevated-metal metal-oxide (EMMO) thin-film transistor (TFT) is proposed that can also act as an etch-stop layer in a high-resolution display stack. 32.3 is a proof-of-concept study, forming polysilicon TFTs on paper, sintering a liquid silicon solution at 100 oC or below.

Next up in 32.4 is Adrien Pierre of UCal. Berkeley, giving an invited talk on “High-detectivity Printed Organic Photodiodes for Large Area Flexible Imagers”, followed by a report on dual-gate a-Si:H fin-TFTs (32.5), which have photosensitivity when operated sub-threshold.

While not conventional TFTs, FD-SOI n- and p-FETs can be light-sensitized by putting a diode in the substrate below the transistors (32.6). The photo-generated carriers in the diode can create a back-bias, shifting the threshold voltage of the transistors. This capability was used to demonstrate a light-controlled SRAM.

Then – lunch! IEDM and IEEE Women in Engineering have organised their annual Entrepreneurs Luncheon, which will feature Vamsee Pamula, co-founder of Baebies, Inc. a company developing digital microfluidics technology for newborn screening and pediatric testing.

In parallel, ASM is hosting their usual Wednesday lunchtime seminar at the Nikko Hotel across the street from the Hilton, this year the topic is “Covering 3D Devices”.

And be back in the Hilton for the afternoon sessions, beginning at 1.30 pm.

Session 33: Process and Manufacturing Technology — Ge Channel Devices

We start with CVD-grown Ge/GeSn/Ge quantum well (QW) p-MOSFETs with transverse uniaxial tensile strain, reportedly giving ~7% mobility enhancement leading to a record high mobility (33.1). The CVD process enables a low thermal budget of 400oC.

The second presentation is invited – Seiichi Miyazaki of Nagoya U. is speaking on “Processing and Characterization of Si/Ge Quantum Dots” (33.2), detailing their research on silicon quantum dots with a germanium core.

Then we explore (33.3) high performance Ge CMOS with quantum well-structured channels a single MoS2 capping layer. The MoS2 confines the carriers within the Ge layer, reducing scattering at the dielectric interface and improving performance.

33.4 demonstrates a silicon-passivated Ge NMOS gate stack, with LaSiO doping at the HfO2/SiO2 interface, that is compatible with 3D structures and has improved PBTI reliability and electron mobility.

The fifth paper of the session discusses Ge finFETs fabricated by neutral beam etching and oxidation, which gives low-defect, smooth surfaces and improved performance compared with conventional reactive ion etching (33.5).

Lastly, there is a description of junction-less GAA n-FETs that use selective laser annealing on epi-Ge on SOI (33.6).

Session 34: Nano Device Technology — Devices Based on Quantum and Resistive Switching Phenomena

Now we get into the realm of quantum dots and qubits; in 34.1 we hear a study of coupled phosphorus donors with MOS quantum dots, giving two-axis control of a two-electron spin logical qubit. 34.2 deals with silicon-based charge qubits with coherence times and operating temperatures two orders of magnitude larger than other reported semiconductor systems.

Nanomagnet networks are explored in 34.3, which are apparently ideal for Ising computing (a method of solving combinatorial optimization problems). VO2 is used for a two-terminal hysteretic voltage switch in 34.4, since it can be voltage-induced to change from metal to insulator and back; in this case it is applied to analogue signal processing.

The same phenomenon is utilised to make low-voltage artificial neurons, that can be voltage-scaled down to 0.3 V (34.5), and threshold switches made with Ag/HfO2 are used as selector switches for PCM-based cross-point memory in 34.6.

Atom-switches (atomic-scale metal-filament switches) are integrated with silicon MOSFETs (34.7) to give ‘atom-switch FETS’ with extremely low leakage current, low operating bias, and sub-threshold swing of less than 5 mV/decade.

The last paper of the day (34.8) presents two dimensional (2D) RRAM devices using multilayer hexagonal boron nitride (h-BN) as the active switching layer; the cyclical release and diffusion of B ions are the key physical mechanisms responsible for switching, forming a boron (B)-deficient conductive filament.

Session 35: Circuit Device Interaction — 3D Systems, Enabling Technologies and Characterizations

This session starts with an invited talk by Fabien Clermidy from CEA-LETI (35.1), reviewing “New Perspectives for Multicore Architectures using Advanced Technologies”, showing how back-end NVM, monolithic 3D integration (CEA-LETI’s CoolCube), and 3D stacking can be used to build more power-efficient systems.

TSMC expands on their InFO (integrated fan-out) technology to build inductors into the stack for integrated voltage regulators to couple with their 16-nm finFET devices (35.2). The InFO substrate was used in volume in the iPhone 7 series, so it will be interesting to see how it has evolved – we already have silicon-based trench capacitors included in the package.

35.3 discusses on-chip high-Q magnetic inductors for power conversion efficiency greater than 90%; 35.4 examines ESD diodes in a bulk GAA-NW process; 35.5 characterizes the hold-time margins of flip-flop arrays across a range of process/temperatures/voltage/aging conditions in Intel’s 22-nm finFET process.

The last presentation models the thermal resistance of the back-end interconnect and finFETs in face-up and face-down formats (35.6).

Session 36: Modeling and Simulation — Materials and Interfaces

The effects of surface roughness scattering (SRS) and how it limits carrier mobility in finFETs and GAA-NW FETs are modelled in 36.1, and the performance improvement in GaN devices given by nitridation is investigated in 36.2.

Manipulating Spin Polarization and Carrier Mobility in Zigzag Graphene Ribbons using an Electric Field” is the topic of an invited lecture by Christophe Delerue of IEMN (36.3). Density functional theory simulations were performed on HfO2/SiOxNy/SiGe stacks with a range of Si/O/N compositions (36.4), and measured experimentally, confirming that lower defect density results from a sub-stoichiometric SiON layer.

36.5 examines PBTI in InGaAs NW-FETS with Al2O3 and LaAlO3 gate dielectrics; simulations seem to show that Al2O3 performs better than LaAlO3.

Contact resistivities in n-type III-V materials are given more extensive modelling in 36.6, indicating higher contact resistivity than earlier models. The last paper (36.7) investigates the transport mechanisms of diamond-like carbon films, since these are now becoming of interest for high-voltage devices. A polarization effect was modelled in a TCAD tool, giving good agreement with experiments.
Chronologically the last paper is due at 4.30 pm – by then a lot of attendees will have headed for home, especially West-coasters who want to get home today.

We should not forget the exhibitors, either – at the time of writing we have:

Cambridge Press

Celadon Systems

Coventor

Everbeing

Global TCAD

GMW Associates

Park Systems

PicoSun

Proplus Design Solutions

Silvaco

Springer

Synopsys

The exhibits are open all three days of the conference, with free coffee available – seeing as there are no coffee breaks during the sessions, it might be good to take time out and change pace in the exhibit area.

I will definitely be suffering from information overload at the end, and becoming brain-numb; but with 233 papers and an average of six parallel sessions at any one time, plus the offsite events, that’s not really surprising. On the other hand, where else do we go to get all this amazing stuff?

Time to unwind, maybe do a little holiday shopping, and go for an indulgent meal.

 

Reference

  • -J. Cho et al., “Si FinFET Based 10nm Technology with Multi Vt Gate Stack for Low Power and High Performance Applications”, VLSI 2016, pp. 12 -13.

IEDM 2016 Next Week!

By Dick James, Senior Technology Analyst, Chipworks

On December 3rd – 7th , the good and the great of the electron device world will make their usual pilgrimage to San Francisco for the 2016 IEEE International Electron Devices Meeting. To quote the conference website front page, IEDM is “is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation.”

That’s a pretty broad range of topics, but from my perspective at Chipworks, focused on the analysis of chips that have made it to production, it’s the conference where companies strut their technology, and post some of the research that may make it into real product in the next few years. Though these days process papers actually tend to be after the launch of the relevant product, such is the preoccupation with trade secrecy.

In the last few weeks I’ve gone through the advance program, and here’s my look at what’s coming up, in more or less chronological order. As usual there are overlapping sessions with interesting papers in parallel slots, but we’ll take the decision as to which to attend on the conference floor.

Saturday/Sunday

Again this year the conference starts on the Saturday afternoon, with a set of six 90-minute tutorials on a range of leading-edge topics:

The first three are from 2.45 – 4.15, and the remainder from 4.30 – 6.00. This year I hope to make it to the Physical Characterization session, and possibly the IoT talk at 4.30.

On Sunday December 14th, we start with the short courses, “Technology Options at the 5-Nanometer Node” and “Design/Technology Enablers for Computing Applications”.

Last year the process short course was “Emerging CMOS Technology at 5 nm and Beyond”, so I guess we will see how things have evolved at 5 nm.

The course has been organized by An Steegen and Dan Mocuta of Imec. They introduce it bright and early, at 8.30 a.m.

The first session is “Nano Patterning Challenges at the 5nm Node”, given byAkihisa Sekiguchi of Tokyo Electron. Next up is Nadine Collaert from imec, discussing “Novel Channel Materials for High-Performance and Low-Power CMOS”, followed by Aaron Thean, of the National University of Singapore (and formerly imec),who is presenting on “Options beyond FinFETs at 5nm node”.

Contacts are the next topic, “Low Resistance Contacts to Enable 5nm Node Technology: Patterning, Etch, Clean, Metallization and Device Performance”, by Reza Arghavani of Lam Research.

The back-end stack gets more critical as dimensions shrink, so we have a review of “Parasitic R and C Mitigation Options for BEOL and MOL in N5 Technology”, by Theodorus Standaert from IBM.

The last session covers off “Metrology Challenges for 5nm Technology”, by Applied Materials’ Ofer Adan – given that we are now counting atoms, challenging is a good way to describe it.

John Chen of Nvidia set up the Design/Technology short course, which takes a fairly high-level look at the technologies involved in processing Big Data, discussing the different processors themselves, the effects of memory, managing the power and connectivity, and where advanced packaging fits in.

So we have:

  • The Rise of Massively Parallel Processing: Why the Demands of Big Data and Power Efficiency are Changing the Computing Landscape” – Liam Madden, Xilinx
  • Breaking the Memory Bottleneck in Computing Applications with Emerging Memory Technologies: a Design and Technology Perspective” – Gabriel Molas, Leti
  • Power Management with Integrated Power Devices…and how GaN Changes the Story” –Alberto Doronzo, Texas Instruments
  • Interconnect Challenges for Future Computing” – William J. Dally, NVIDIA/ Stanford U
  • Advanced Packaging Technologies for System Integration” – Douglas Yu, TSMC

I would call both courses a full day, seeing as we finish at ~5.30 p.m., but it’s worth sticking around to the end.

If you have the stamina, at 6.00 CEA-Leti is hosting a Devices Workshop at the Nikko Hotel, across the street from the Hilton.

Monday

Monday morning we have the plenary session, with three pertinent talks on the challenges and potential of contemporary electronics:

  • “Technology Scaling Challenges and Opportunities of Memory Devices” – Seok-Hee Lee, Hynix
  • “Brain-Inspired Computing” Dharmendra S. Modha – IBM
  • “Symbiotic Low-Power, Smart and Secure Technologies in the age of Hyperconnectivity” – Marie-Noëlle Semeria, Leti

Three quality presentations in three hours, but beware of numb bum if you take in all of them – get up and have a stretch in between, and take a walk before lunch!

After lunch, in keeping with IEDM’s tradition of intellectual overload, we have seven parallel sessions!

Session 2: Circuit and Device Interaction — Advanced Platform Technologies – including 7 nm finFETs!

Session 2 starts a track on Circuit and Device Interaction, in this case with papers on Advanced Platform Technologies – for me a highlight session, since the session ends with duelling 7-nm late-news papers from TSMC (2.6) and the Samsung/GLOBALFOUNDRIES (GF)/IBM consortium (2.7).

In addition, we have a GF/Leti discussion of the GF 22FDX SOI technology (2.2) announced last year; paper 2.3 is a research paper on 3D monolithic integration of ultra-thin body MOSFETs into a VCO and power management circuit, with a 4-layer Vertical ReRAM, by Taiwan’s National Nano Device Laboratories and National Chiao Tung University.

GF co-authors the next two papers, detailing a high-resistance SOI technology for RF front-end modules (2.4), integrating a power MOSFET with a RF switch by using selective silicon thinning; and (2.5) a look at monolithic 3D IC design partitioning to mitigate the performance limits set by the limited thermal budget of the upper transistor level in the 3D IC stack.

In 2.6, TSMC announces the “world’s first 7nm CMOS platform technology for mobile system-on-a-chip (SoC) applications, featuring FinFET transistors”. They claim the world’s smallest-ever SRAM cell at 0.27 µm2, and 3x the gate density of the 16-nm process, together with a 35 – 40% speed gain or over 65% power reduction.

In addition, the process uses 93nm immersion lithography, raised source/drain epi, a novel contact technique, and a 12-layer copper/low-k interconnect stack.

By contrast, the finFETs in 2.7 from the GF/IBM/Samsung group consortium (presumably at Albany, NY) were manufactured using EUV, with contacted polysilicon pitch (CPP) of 44/48nm, and metallization pitch of 36nm. It also features dual-strained channels formed on a thick strain-relaxed buffer (SRB) virtual substrate to give tensile-strained NMOS and compressively strained SiGE PMOS for the enhancement of drive current by 11% and 20%,  respectively, when compared with a common planar (my italics) HKMG process. Epitaxy is used in the contact trenches to minimize resistance.

Schematic (center) of dual-stressed channel materials on the SRB with a super-steep retrograde well (SSRW), along with TEM images of (a) the tensile-strained silicon fin and (b) the compressively-strained SiGe fin on a common SRB (2.7).

Schematic (center) of dual-stressed channel materials on the SRB with a super-steep retrograde well (SSRW), along with TEM images of (a) the tensile-strained silicon fin and (b) the compressively-strained SiGe fin on a common SRB (2.7).

Session 3: Compound Semiconductor and High Speed Devices — Compound Semiconductors for High Speed RF and Low Power Logic Applications

The session starts with a paper (3.1) from Germany’s IHP Institute, on their (claimed) fastest silicon-based heterojunction bipolar transistor (HBT), with an fT/fmax of 505 GHz/720 GHz, respectively, at 1.6 V; they attribute this to optimized vertical profiles of the emitter-base-collector regions, the use of “flash” annealing and low-temperature backend processing to lower base and emitter resistance, and lateral device scaling.

TEM image of a cross-section of an optimized Si HBT device (3.1).

TEM image of a cross-section of an optimized Si HBT device (3.1).

Lund University is up next (3.2), discussing InGaAs tri-gate MOSFETs with record on-current of 650 µA/µm at 0.5 V. Paper 3.3 is an invited talk on “High Frequency GaN HEMTs for RF MMIC Applications”, from HRL Labs.

In paper 3.4, MIT studies a new form of instability due to F- migration and the passivation/depassivation of Si dopants in a n-InAlAs cap layer in InGaAs MOSFETs; it turns out that removing the cap layer gets rid of the instability!

MIT also presents paper 3.7, on using a physical compact model to improve the RF circuit linearity performance of GaN HEMTs, in both device and circuit design techniques. GaN HEMTs are again discussed in 3.5, this time W-band N-polar devices; UCal Santa Barbera claims a record high efficiency of 27.8% at 94 GHz.

And to fill in the gap at 3.40 pm (3.6), IBM gives an invited talk on “Monolithic Integration of Multiple III-V Semiconductors on Si for MOSFETs and TFETs”, using template-assisted selective epitaxy (TASE) for a number of III-V compounds.

Session 4: Memory Technology — RRAM, PRAM and Applications

We start with an invited talk “Towards Ultimate Scaling Limits of Phase-Change Memory” (4.1) by Feng Xiong of Stanford U., reviewing advances in phase-change memory (PCM), which is now down to sub-10 nm scale, with switching energies approaching femtojoules per bit.

Paper 4.2 discusses confined ALD-based PCM with a metallic liner, which is reported to have record endurance of 2e12 cycles; and 4.3 looks at SiOx-based RRAM (Resistive Random-Access Memory) in crossbar memory arrays, and also as select devices in the arrays.

Oxygen implantation into Ta2O5 and HfO2 is used to form RRAM devices in the ON state (4.4), which subsequently switch similarly to regularly made reference devices. The correlation between endurance, window margin and retention of RRAM types (oxide RAM and conductive bridge RAM) is studied in 4.5, and the effect of programming parameters on oxide RAM retention is the topic in 4.6.

The intrinsic variability factors of RRAM are quantified in 4.7, to identify the fundamental variability limits of the technology, and the last paper (4.8) details a random number generator fabricated in Panasonic’s 40-nm embedded ReRAM process.

Session 5: Nano Device Technology — 1D and 2D Devices

This session (not surprisingly) is a set of research papers, starting with a pair of carbon nanotube (CNT) transistor studies; 5.1 details CNT-FETs with nickel contacts alloyed into the ends of the CNTs to reduce contact resistance and give scalability to the contact process.

Schematic of a CNT-based CMOS inverter with entirely Ni end-bonded contacts (5.1)

Schematic of a CNT-based CMOS inverter with entirely Ni end-bonded contacts (5.1)

We look at vertically suspended CNT-FETs in 5.2, which allows a fully gate-all-around (GAA) structure with multiple channels, optimising gate controllability and enhancing charge transport.

In 5.3 we move to graphene FETs, again examining ways of reducing contact resistance, this time using “atomic orbital overlap engineering”.

Paper 5.4 is an invited talk from Mathieu Luisier of ETH Zurich on simulations of 2-D devices, reviewing mobility, I-V characteristics, and contact resistance, with extra detail on contacts to molybdenum disulphide (MoS2).

Black phosphorus is another potential 2-D transistor material, and PMOSFETs with a boron nitride/alumina gate dielectric are discussed in 5.5.

The last three papers focus on MoS2, examining 10-nm top-gated transistors in 5.6, and we go beyond transistor studies in 5.7 to develop guidelines for co-optimisation of material, devices, and circuits, to get the yield up and move towards manufacturability. The final paper (5.8) gets back into the detail of the MoS2 MOS interface trap density created by S vacancies in the MoS2.

Session 6: Sensors, MEMS, and BioMEMS — Focus Session: Wearables for the Internet-of-Things (IoT)

As a focus session, this features a series of seven invited presentations;

  • High Performance, Flexible CMOS Circuits and Sensors Toward Wearable Healthcare Applications,” by K. Takei, Osaka Prefecture University (6.1)
  • Circuits and Systems for Energy-Efficient Smart Wearables,” by A. Sharma, Texas Instruments (6.2)
  • Flexible Metal-Oxide Thin-Film Transistor Circuits for RFID and Health Patches,” by P. Heremans et al, Imec/University of Leuven/Holst Centre (Belgium)/National Centre for Flexible Electronics (India) (6.3)
  • Challenges and Opportunities in Flexible Electronics,” by R. D. Bringans and J. Veres, Xerox PARC (6.4)
  • Advanced Integrated Sensor and Layer Transfer Technologies for Wearable Bioelectronics,” by D. Shahrjerdi et al, New York University (6.5)
  • Wearable Sweat Biosensors,” by A. Javey et al, University of California, Berkeley (6.6)
  • Flexible Metamaterials, Comprising Multiferroic Films,” by Y. P. Lee et al, Hanyang University (6.7)
Schematics and example of wearable sweat sensor from paper 6.6

Schematics and example of wearable sweat sensor from paper 6.6

Session 7: Modeling and Simulation — Advanced Numerical and Compact Models

The first paper details an electro-thermal compact model for self-heating ICs, including the BEOL, that can predict front-and back-end reliability, and takes account of interconnect layout and geometry (7.1).

In 7.2 we hear about a model that considers the percolation path of the channel current in a transistor to help understand the statistical variability and reliability in nanoscale devices, and compares the different features of 3-D finFETs with planar transistors.

HfOx-based analog synaptic devices are considered in 7.3; the SET, RESET, and retention loss processes are simulated and given experimental verification, capturing the key material parameters and forming optimization guidelines.

P-channel GaN MOSHFETs are the topic in 7.4, examining the electric field distribution to determine why a higher threshold voltage needs reduced channel and oxide layer thicknesses. This led to the introduction of an AlGaN cap layer to modulate the field and increase the on-current.

We move to GAA-MOSFETs in the next presentation, modelling stacked-planar and vertical transistors of circular, square, and rectangular cross-sections (7.5). Then we change technologies again and look at the resistive switching behaviours of CBRAM devices (7.6).

CBRAMs use the property that if amorphous insulating materials contain a relatively large amount of metal, the metal ions they contain can form a conductive path when voltage is applied; this can be reversible, enabling the storage of data as the conductor appears and disappears. The paper studies three modes of filament formation.

3-D cross-point memory cells formed using germanium-selenium telluride (GST) are discussed in the last paper of the session (7.7), extending the model to simulate memory array circuits.

Session 8: Optoelectronics, Displays, and Imagers — Imaging and Photon Counting Sensors

The first paper in the session presents a backside-illuminated (BSI) single photon avalanche diode (SPAD) image sensor (8.1), a claimed first in the field. Most of the CMOS image sensors (CIS) in smartphone cameras these days are BSI, usually with stacked dies and through-silicon vias (TSVs), although the very latest use face-to-face wafer bonding of the metal interconnects.

It looks as though this device also uses stacked dies, since the SPADs are fabbed in a 65-nm process, and the processor is 40-nm.

SPADs are getting attention lately since they are also appearing in mobile phones in time-of-flight auto-focusing devices for the cameras, and in the latest iPhone they are doing double duty as a proximity sensor and autofocus for the selfie camera; see my last blog for more details.

STMicroelectronics time-of-flight sensor from iPhone 7

STMicroelectronics time-of-flight sensor from iPhone 7

Paper 8.2 is also focused on SPADs, in this case a 256 x 256 image sensor with 16 µm pixel pitch and a 61% fill factor. Then we have an invited talk from M.Mori of Panasonic (8.3), discussing “An APD-CMOS Image Sensor Toward High Sensitivity and Wide Dynamic Range”; followed by Sony (8.4) showing off their latest die stacking using copper/copper hybrid bonding connecting the image sensor to the image processor (also known as direct bond interconnect (DBI).

We at Chipworks actually found this technology in the Samsung Galaxy S7 Edge back in March, so it is definitely in volume production.

SEM cross-section of Sony image sensor from Samsung Galaxy S7 Edge, showing copper/copper direct bonding

SEM cross-section of Sony image sensor from Samsung Galaxy S7 Edge, showing copper/copper direct bonding

Next up is a global shutter CIS (8.5) which somehow has 480 analog memories/pixel integrated using vertical analog memory technology, which enables 1 Mfps.

In 8.6, Canon exhibits one of their huge 35-mm full-frame sensors, this time a low-noise global shutter device with a 6.4 µm pixel size. Apparently, most CMOS imagers use a rolling shutter, which reads the pixels at different times at different parts of the imager, leading to image artifacts, especially for moving targets (see image below of vibrating ukulele strings).

8.6 Canon

 
The last paper is another from Sony (8.7), this time detailing a “Four-Directional Pixel-Wise Polarization CMOS Image Sensor Using Air-Gap Wire Grid on 2.5-µm Back-Illuminated Pixels”. If I understand the abstract correctly, this sensor has a wire grid with 150-nm pitch over the pixels which acts as a polarizer, presumably in the four directions of the grid sides.

That is the end of the Monday afternoon sessions, and the reception will start at 6.30 pm in the Grand Ballroom; but if you have links to Stanford U, there is a gathering at 5 before then.

Tuesday

Session 9: Process and Manufacturing Technology — 3D Integration and BEOL

The session starts (9.1) with a discussion of 3D-stackable finFETs compatible with back-end processing, using single-grained silicon fins and laser spike anneal to keep the thermal budget down.

We have seen the use of liquid surface tension for die positioning and self-assembly in years past; in 9.2 we have it applied to 2.5/3D integration of multiple types of die, even those with uneven surfaces and bottom topography.

Next we have an invited presentation (9.3) by Ruth Brain of Intel, on “Interconnect Scaling: Challenges and Opportunities”, focusing on the transistor/interconnect optimization that is necessary now that interconnect delay is dominating circuit performance.

Paper 9.4 looks at a high-k MIM decoupling capacitor aimed at the 7-nm node; and 9.5 discusses graphene-on-copper for improved interconnectivity and enhanced electro-migration lifetime. The last paper (9.6) explores the intriguing concept of vertical-channel devices gated by TSVs.

Session 10: Power Devices — Power Semiconductor Device Technologies

We get into the world of GaN devices in the first four papers – 10.1 details a normally-off V-trench GaN transistor formed on a GaN substrate, with a record 1.7 kV breakdown voltage and on-state resistance of 1.0 mΩcm2; 10.2 describes a vertical GaN Schottky rectifier incorporating trench MIS structures and field rings; 10.3 is about GaN gate injection transistors with high-speed switching, again built on a GaN substrate; and 10.4 presents on high-performance enhancement-mode GaN MIS-FETs with a recessed-gate structure and a SiNx gate dielectric.

Schematic cross-section of lateral p-type GaN transistor with slanted channel (10.1)

Schematic cross-section of lateral p-type GaN transistor with slanted channel (10.1)

Next we have an invited talk (10.5) on “Superior Performance of SiC Power Devices and Its Limitation by Self-heating” by T. Terashima of Mitsubishi Electric, followed by a paper looking at the 3D scaling of IGBTs (10.6), giving lower on-resistance.

The last two papers go back to SiC devices, with a description of a vertical p-type SiC MOSFET with enhanced breakdown voltage (10.7), and 10.8 is a study of hysteresis in subthreshold drain current in SiC n-MOSFETs, caused by hole capture in border traps.

Session 11: Memory Technology — Charge Based Memories and Scaling

In this second session of the Memory track, we move to other forms of memory and embedded memory. Renesas and Hitachi have worked out a way to build split-gate MONOS flash on finFETs (11.1); then Samsung gives an invited review “A New Ruler on the Storage Market: 3D-NAND Flash for High-density Memory and its Technology Evolutions and Challenges on the Future” (11.2). We have seen 3D-NAND flash go from 24 – 32 – 48 – 64 layers in the last four years, and all four of the flash manufacturers are now in volume production; this review should cover off that evolution, as well as discuss some of the challenges as the process complexity increases.

Macronix has stated that they plan to join the 3D-NAND business, and in 11.3 they study instability caused by the grain boundaries in the polysilicon channel of vertical flash structures. Another invited talk is next, this time by Bosch (11.4), discussing the qualification of non-volatile memories (NVM) for automotive applications, and the resulting requirements for the NVM supplier, and the implications for design and technology of NVMs.

Paper 11.5 is a study of a ferroelectric transistor (FeFET) based eNVM retrofitted into GLOBALFOUNDRIES’ 28SLP HKMG process using an extra layer of SiHFO inserted into the transistor gate stack.

TEM cross-sections of GF 28SLP transistors (left), and FeFET device (right), showing the extra SiHfO layer (11.5)

TEM cross-sections of GF 28SLP transistors (left), and FeFET device (right), showing the extra SiHfO layer (11.5)

The next paper (11.6) has an intriguing abstract – how to convert ZrO2-based DRAMs (i.e. most DRAMs) into NVMs – I look forward to the details! The last talk details a tantalum-oxide based selector device that can be formed in a crossbar array, and fitted into the back-end process sequence (11.7).

Session 12: Nano Device Technology — Negative Capacitance and New Material MOSFETs

In this session we have a series of papers on ferroelectric negative capacitance (NC) devices, mostly using HfZrOx. The first describes a NC-finFET with a 1.5-nm thick HfZrOx layer (12.1), then we have HfZrOx germanium (Ge) and Ge-tin p-MOSFETs (12.2), followed by a study on a HfO2 NC-FET, looking at its polarization-limited operating speed (12.3).

12.4 simulates sub-10-nm NC-finFETs, showing excellent short-channel performance; 12.5 examines InGaAs MOSFETs with a La2O3 dielectric, revealing that La2O3 can have ferroelectric properties, and can be used to form NC-FETs; and 12.6 analyzes the hole and electron effective masses in the inversion layers of Ge (100), (110) and (111) p- and n-MOSFETs.

Session 13: Optoelectronics, Displays, and Imagers — Focus Session: Quantum Computing

This Focus Session features invited papers describing several technologies to fabricate quantum bits (qubits), including transmon qubits, spin qubits in silicon, and FDSOI qubit technology with silicon nanowire field-effect transistors. There are also discussions of quantum technologies based on luminescent crystalline defects in diamond, and the prospects of scalability, considering the potential fabrication of large-scale systems with millions of qubits.

  • Quantum Computing Within the Framework of Advanced Semiconductor Manufacturing,” by J. S. Clarke et al, Intel/TU Delft
  • Spin-Based Quantum Computing in Silicon CMOS-Compatible Platforms,” by A.S. Dzurak, University of New South Wales
  • Coupled Quantum Dots on SOI as Highly Integrated Si Qubits,” S.Oda, Tokyo Institute of Technology
  • SOI Technology for Quantum Information Processing,” by S. De Franceschi et al, CEA/University Grenoble Alpes
  • Cryo-CMOS for Quantum Computing,” by E. Charbon et al, Delft University of Technology/EPFL/Institut Superieur d’Electronique de Paris/Tsinghua University/Univ. California, Berkeley
  • Diamond–A Quantum Engineer’s Best Friend,” by Marko Lončar, Harvard University
  • Large-Scale Quantum Technology Based on Luminescent Centers in Crystals,” by M. Trupke et al, TU Wien/University of Vienna/Nippon Telegraph and Telephone/National Institute of Informatics (Japan)

Session 14: Modeling and Simulation — 2D Materials and Organic Electronics

Back in session 5 we had some MoS2 papers, and 14.1 is a study on two MoS2 transistor types, a lateral heterostructure FET and a “planar barristor”; then we have an invited review (14.2) of “Physics of Electronic Transport in Two-dimensional Materials for Future FETs” by Massimo Fischetti from U. Texas (Dallas).

Next up is an atomic-scale simulation of silicon contact with MoS2 (14.3), and 14.4 is an examination of graphene/semiconductor contacts for a range of materials. Paper 14.5 predicts the performance of InAs, InN, InP and InSb double-gate, single-layer n- and p-type transistors; and 14.6 is an invited review of the “Current Status and Challenges of the Modeling of Organic Photodiodes and Solar Cells”, by R.R. Clerc of the Institut d’Optique Graduate School.

The session finishes with a discussion of ultra-thin nanowire gated 2D-FETs, focusing on dielectric growth and channel formation (14.7). In one example, a thin (6nm) conformal Al2O3 dielectric was formed around Co2Si nanowires on a carrier wafer, and were then gently pressed against a MoS2 substrate to transfer them – this avoids having to deposit the dielectric on the MoS2. The curvature of the nanowire ensures that only a short section of it is in contact with the 2D layer, creating a short channel length.

Schematic illustration of a nanowire-gated 2D FET (left), and TEM cross-section of a fabricated device (14.7)

Schematic illustration of a nanowire-gated 2D FET (left), and TEM cross-section of a fabricated device (14.7)

Session 15: Characterization, Reliability and Yield – FINFET and Nanowire Device Reliability

Samsung is first up this session, characterizing the reliability of their 10-nm process technology (15.1). They presented the basics of it at VLSI at VLSI this year [1]; they described it as:

“Fin and dummy Si gate were defined by sidewall image transfer using a mandrel and sidewall space. 3rd generation Fin features more vertical and thinner shape than previous technologies, which allows for stronger control of the short channel effect. Highly doped S/D with 3rd generation epitaxial process is combined with advanced contact process to boost performance. Copper interconnects were fabricated using conventional immersion bi-directional patterning and CVD-liner process.”

And these are some of the design rules:

Samsung VLSI

In addition to reliability studies, the paper will describe describe process optimizations that overcome problems such as self-heating effects caused by the taller and narrower fin shape.

TSMC contributes an invited talk (15.2) on a similar topic “Consideration of BTI Variability and Product Level Reliability to Expedite Advanced FinFET Process Development”, and we get into serious detail in 15.3 with a statistical model of NBTI degradation of p-finFETs.

IBM reports on hot-carrier reliability in gate-last SiGe-channel p-finFETs in 15.4, and we have a post-mortem study of dielectric breakdown in finFETs in 15.5, including TEM/EELS/EDX analysis; and, according to the abstract “The assumption that the kinetics of failure would remain the same for both planar and FinFET devices is proved to be untrue.”

15.6 is an imec review of self-heating in finFETS and gate-all-around nanowires (GAA-NWs), and 15.7 continues the theme, exploring thermally-aware transistor design to reduce self-heating of floating-body devices such as FD-SOI, SOI-finFETS, and GAA-NWs.

We finish with an invited presentation (15.8) on nano-thermometry, using an AFM-based tool to look at localized hot spots in nano devices.

Session 16: Circuit and Device Interaction – Resistive Device Designs for von-Neumann Computing and Beyond

One of the trends in recent years has been the application of resistive RAM for neuromorphic computing; it appears that RRAM memories have the advantage in that they can hold a range of resistive states that can correspond to the “shades of grey” in human thinking.

The second session in this track continues that theme. The first paper examines the use of vertical RRAM for language recognition (16.1). Here, the RRAM is vertically oriented, whose physical structure corresponds to the team’s hyper-dimensional computing algorithm. This 3D-VRRAM allowed the computing framework to recognize words in 21 different languages from sample texts.

The next paper (16.2) details a binary neural network using 16-Mb RRAM devices for image recognition; 16.3 discusses a novel non-volatile flip-flop with a single RRAM NVM included; 16.4 describes a 50 x 20 crossbar switch block with two a-Si/SiN/a-Si varistors for non-volatile FPGAs; and a 4-transistor NV-SRAM with two RRAMs (4T2R, instead of the usual 6T SRAM cell) is fabricated in TSMC’s 40-nm process in 16.5.

16.6 is a higher-level study of a fully connected neural network using arrays of OxRAM devices, and applying short- and long-term plasticity rules, suitable for (e.g.) visual pattern extraction from highly noisy data.

Image reconstruction is used as a diagnostic tool to evaluate the device variability in memristor crossbar arrays in 16.7, and 16.8 demonstrates unsupervised learning by spike-time dependent plasticity (STDP) and spike-rate dependent plasticity (SRDP) in neural networks using CMOS-based RRAM synapses.

Finally, it’s time for lunch! This year’s speaker at the conference lunch is Prof. Roberto Cingolani from the Istituto Italiano di Tecnologia in Genoa, Italy, presenting on “Translating evolution into technology: from biochemical robots to autonomous anthropomorphic machines”. We are used to the concept of living creatures evolving over time – here we will have a comparison between living and artificial systems, and the attempts to reproduce the characteristics of living things using technology.

Tickets are available online when you register – if you haven’t, there are usually some at the conference front desk. The afternoon sessions start again at 2.15.

Part 2 of the preview will be up in a few days, before the conference!

ST Micro electronics Time-of Flight Sensors and Starship Enterprise Show up in the iPhone 7 Series

By Dick James, Senior Technology Analyst, Chipworks

One of the lesser-known stories of mobile phone evolution is the development of proximity sensing in order to save power and disable touch-screen functions when the phone is actually being used as a phone. This essentially means turning off the screen (and the touch-capability tasks) when the phone is brought up to the ear.

In the very early days there was no such thing; then a simple photodiode was used to sense the change in light level. This worked in most circumstances, but under certain conditions (e.g. an old guy with a white beard) it didn’t, to the embarrassment of the manufacturers. With the screen on, of course, the touch function still works, and an inadvertent touch could hang up the call. Apparently the iPhone 4 got a bad name for this particular fault.

So active systems were introduced, usually with an LED in combination with light sensors to sense the change in light as the phone comes to the face, and then confirm facial proximity with active illumination from the LED. If the proximity sensor receives reflected light above a pre-defined threshold level, it turns the screen off; and of course this threshold level has to be set so that it functions in close to 100% of situations, irrespective of the reflectance of the adjacent surface.

Now we are seeing a further step in the sequence in the transition from the iPhone 6s to the iPhone 7. The 6s used the LED + sensors option, but the iPhone 7 appears to have gone to the next stage and introduced a time-of-flight (ToF) sensor.

The advantage of ToF is that is doesn’t depend on reflected light level – it actually measures the time of travel of photons emitted from a laser diode, and this travel time is independent of the reflectance of the target surface.

Fig 1

We first saw a ToF sensor in the Blackberry Passport, which introduced us to the concept, and the STMicroelectronics VL6180. This is a three-in-one smart optical module, incorporating a proximity sensor, an ambient light sensor, and a VCSEL light source. We subsequently found it in a few more phones:

Fig 2

The proximity sensor is actually an array of single photon avalanche diodes (SPADs), which fortunately can be integrated into a regular CMOS process.

Fig 3

The VL6180 actually has two SPAD arrays on-die, together with the ambient light sensor:

Fig 4

The VCSEL is co-packaged with the die to give the complete unit.

In January, ST announced its second-generation sensor, the VL53L0, which we also found in half a dozen phones this year, all from the Asia-Pacific region (don’t forget that Motorola is now Lenovo).

Fig 5

Both of these were used as range-finding devices for the primary camera, not as proximity sensors for phone operation. The VL53L0 has dispensed with the ambient light sensor, and the SPAD arrays have been modified.

Fig 6

Now we get to the iPhone 7 – when we looked at the selfie camera side, and took out the sub-assembly, both the ambient light sensor and the LED/sensor module were different from those in the 6s model.

Fig 7

When we take them off and look at the module, it looks very ST-ish:

Fig 8

And when we get the die out, it is not the same, but definitely is similar style and die numbering (S2L012AC) to the VL53L0/S3L012BA die, with the two SPAD arrays, and this time the VCSEL is bonded on top of the ToF die to give a very compact module.

Fig.9

So we think we can come to the conclusion that the proximity sensor is now a ToF sensor – and it can also act as an accurate rangefinder for the selfie camera. Nothing announced by either Apple or STMicroelectronics, but yet another of the subtle improvements that we see in the evolution of mobile phones. It was also in the 7 Plus, so a good design win for ST.

We also looked at the ambient light sensor, which was actually the same as in the iPhone 6s, and looks fairly conventional. We don’t know who makes it, but it does have Star Trek’s Starship Enterprise on board!

Fig 10

Samsung’s Galaxy Note 7 is More Than the Batteries!

By Dick James, Senior Technology Analyst, Chipworks

As usual, within days of the August 19 launch of the Samsung Galaxy Note 7, we had it in pieces and had identified most of the significant components that were inside.

01Chipworks-teardown-techinsights-samsung-galaxy-note7

 

APU and memory

The application processor that drives our phone is the Exynos 8 Octa (Exynos 8890), similar to the Galaxy S7 and S7 edge. It has an eight-core CPU, with four Samsung-designed M1 cores that can run at 2.3 GHz, and four ARM Cortex A53 cores operating at up to 1.6 GHz. The graphics side of the chip uses an ARM Mali-T880 MP12 GPU (with 12 graphics cores). It has a LTE Category12/13 modem and is made with their latest 14LPP finFET process.

02Chipworks-teardown-techinsights-samsung-galaxy-note7-ARM Mali T880MP12...

 

Stacked on top of the CPU in the usual package-on-package (PoP) stack, is 4 GB of Samsung LPDDR4 SDRAM. Now that we have 20 nm DRAM processes, the dies are small enough that they are packaged in a 2 x 2 x 2 configuration. Here is the plan-view X-ray image showing the wire bonding of the memory chips. The four stacks of two 4-Gb memory dies are mirror-imaged, on both the vertical and horizontal axes.

03Chipworks-teardown-techinsights-samsung-galaxy-note7-ARM Mali T880MP12...

 

The dies are just about square (5.4 x 5.1 mm); the use of two-die stacks reduces the package thickness to 0.5 mm. This may be the first time we have seen this particular layout.

The 64 GB of flash memory was supplied by a Toshiba THGBF7G9L4LBATR UFS 2.0 part, fabricated using the latest 15 nm generation process.

Cameras

There are three cameras in the Note 7: the usual front- and rear-facing units and an extra one for the iris-scanning security feature of this phone. The main camera is 12 MP with optical image
stabilization (OIS) provided by a STMicroelectronics L2GIS 2-axis gyroscope, the middle chip in this picture:

04Chipworks-teardown-techinsights-samsung-galaxy-note7-STM-design-win

 

The selfie camera is a 5 MP Samsung part and the iris scanner is also Samsung-made, but we have not yet characterized it as to size and technology.

05Chipworks-teardown-techinsights-samsung-galaxy-note7-selfie-camera

 

Sensors

STMicroelectronics supplies all the MEMS motion sensors in the Note 7. In addition to the OIS sensor, there is a LPS25HB pressure sensor and a LSM6DS2 6-axis gyroscope/accelerometer module. All of these have many design wins in phones and wearables.

06Chipworks-teardown-techinsights-samsung-galaxy-note-7-sensors-stmicroe...

 

In addition to the motion sensors, there is an infrared proximity sensor, a heart-rate sensor, and the now ubiquitous fingerprint sensor. The proximity and heart rate sensors appear to be Samsung products, while the fingerprint sensor is reported to be from Synaptics.

RF front end

The RF front end in a phone these days is a very complex thing. The connectivity specification covers a multitude of bands (2G, 3G, 4G LTE-A), as well as Wi-Fi (802.11 a/b/g/n/ac), Bluetooth v4.2, GPS, A-GPS, GLONASS, BDS, GALILEO, NFC, and wireless charging.  It’s no wonder that we have quite an inventory of parts in that area of the phone:

Component Manufacturer Part Number
Antenna Switch Modules Murata 312
  Murata 317
  EPCOS D5287
Envelope Tracking Power Supply Samsung SHANNON 735
Front End Module Skyworks SKY78048-12
GPS Broadcom BCM4774IUB2G
NFC Controller Samsung 81DGXS1
Power Amplifier Modules Avago AFEM-9030
  Avago AFEM-9030
RF Transceiver Samsung SHANNON 935
Wireless Charging IDT IDTP9221S
WiFi Module Murata KM6608027

Touch controllers

The touch control function seems to be distributed in the Note 7, possibly since we also have the S-Pen capability. There is a Cypress CY8CMBR3145 CapSense® Express™ controller, a Samsung S6SY661X, and a Wacom W9018 digitizer, which apparently assesses the different pressure levels applied by the S-Pen to the screen.

07InsideTechnology-Chipworks-teardown-techinsights-samsung-galaxy-note-7...

 

Power management

As with every other smartphone, there are multiple power management ICs (PMICs), in this case five:

08InsideTechnology-Chipworks-teardown-techinsights-samsung-galaxy-note-7...

And what about the batteries?

It’s now well known that, due to some phones exploding or catching fire while being charged, Samsung has launched a recall of the millions of Note 7s already shipped. On their UK website, they clarified that “An overheating of the battery cell occurred when the anode-to-cathode came into contact, which is a very rare manufacturing process error.” In other words, something in the battery shorted out, likely because a separation membrane within the battery was defective.

The problem takes me back to the New Year (after Christmas), when there was a spate of hoverboards catching fire – they also use lithium-ion (Li-ion) batteries, only bigger. As a consequence, K.M. Abraham of Northeastern University published a useful explanation of what happens when Li-ion batteries fail.

“It is safe to say that these well-publicized hazardous events are rooted in the uncontrolled release of the large amount of energy stored in Li-ion batteries as a result of manufacturing defects, inferior active and inactive materials used to build cells and battery packs, substandard manufacturing and quality control practices by a small fraction of cell manufacturers, and user abuses of overcharge and over-discharge, short-circuit, external thermal shocks and violent mechanical impacts. All of these mistreatments can lead Li-ion batteries to thermal runaway reactions accompanied by the release of hot combustible organic solvents which catch fire upon contact with oxygen in the atmosphere.

The specific heat of a typical Li-ion cell has been measured experimentally to be 1 joule per degree Kelvin per gram. A state-of-the-art 18650 Li-ion cell with 3.2 Ah capacity and an average voltage of 3.6V produces 11.5 Wh (41400 Joules) of energy. The weight of the 18650 cell is about 46 grams.

We can calculate that the 41400 Joules of heat will raise the temperature of the 46 gram cell by 900 °C under adiabatic conditions if a short-circuit or another event causes a thermal runaway reaction. That means that if an 18650 Li-ion cell operating at 20 °C short-circuits its temperature under adiabatic conditions can rise as high as 920 °C.”(!!)

Below is a picture of the battery in the phone we dismantled (left), and it’s 3500 mAh (= 3.5 Ah), and 4.4 V, so we have 15.4 Wh of energy in it, 34% more than the unit quoted above; we don’t know the weight, but clearly your phone could get up to ~900 oC or more if the battery is faulty.

Note the “Cell Made in China, Assembled in Vietnam” on the battery. Out of curiosity, we checked out the iFixit teardown of the Note 7, and noted that their phone had a different battery (right).

09Chipworks-teardown-techinsights-samsung-galaxy-note-7-batteries

 

The iFixit phone reads only “Made in China”, so there are two battery sources. If you look closer, model EB-BN930ABE (left) is from Vietnam, and model EB-BN930ABA (right) is the Chinese version.

The Korea Herald added a bit more detail and confirmed the two battery sources as company affiliate Samsung SDI, supplying 70% of Note 7 batteries, and Chinese company ATL, supplying the remaining 30%.

The whole issue is further complicated by the non-removable nature of the batteries in the phone, necessitating a full recall. Unfortunately, we can no longer send ours in to get it replaced!

Soitec Bounces Back, Makes Gains in Mobile Phones, Automotive

By Dick James, Senior Technology Analyst, Chipworks

July 11 – 15 was the week for the annual pilgrimage down to the SEMICON West show, though it’s becoming less of a show these days than a gathering place for the industry, with multiple conferences in parallel. Hence the motto for the event, “Definitely Not Business as Usual.”

Semicon

Of course there were exhibitors, some 700+ I’m told, and we’ll have to wait for the post-show release to see how many attendees. From my observation, things were busy without being hectic on the show floor, and there was the usual slew of press releases and social media postings from both exhibitors and attendees.

One such was a tweet from the French wafer manufacturer Soitec, which specialises in SOI wafers, having pretty well cornered the market with the success of their Smart Cut™ technology. They announced a “new identity”, complete with a new logo, in time for the show and in advance of their AGM on July 25.

While I was at SEMICON West I had the chance to meet with Camille Dufour and Tom Piliszczuk of Soitec – we have seen increasing amounts of SOI devices in the phones that we analyze, so I was curious to find out what their range of materials was and what markets they were targeting. We have all followed the finFET/FDSOI debate in the last few years, and some still doubt that FDSOI will take off; but RFSOI and power SOI are making steady gains in the wireless and automotive sectors.

The logo change is straightforward enough:

Soitec logos

The “new identity” reflects a structural change within Soitec in the last year or two. A while back Soitec had decided to leverage their Smart Cut and Smart Stacking techniques to get into the solar cell and lighting businesses. Technologically they did quite well, getting to almost 50% efficiency for solar cells; but they were targeting the concentrated photovoltaic (CPV) market, which turned out to be a much more niche market than they anticipated.

Consequently the balance sheet started to suffer, to the point where some of their customers questioned the viability of the company. So at the beginning of last year the decision was taken to get out of the PV and lighting businesses, and focus on their core business of electronic materials. They also sold off their Altatech equipment subsidiary to Fogale Nanotech.

By the middle of this year all of the financial details were cleared up, and Soitec came back into operating profit. There was still a bit of a financial hangover from the discontinued operations, so a capital investment was arranged and a chunk of the company’s debt was paid off.

All of which is a roundabout way of saying that Soitec now regards itself a re-generated company based solely on the manufacture of electronic materials, so worth an announcement in time for Semicon West, the prime event for semiconductor materials suppliers.

If you peruse the products section of the website, you will see they sell four streams of SOI wafers:

  • Digital SOI, which covers off partially-depleted and fully-depleted SOI (PD-SOI and FD-SOI)
  • RF-SOI
  • Power SOI
  • Photonics SOI

Digital SOI is in a bit of a holding pattern right now; PD-SOI is in a slow decline as legacy game console parts and AMD processors fade away, and though IBM is still using PD-SOI for its Power series of processors, that is a fairly niche business and unlikely to consume huge volumes of wafers. (IBM once had the bulk of the game chip business, making chips for Microsoft, Sony, and Nintendo.)

When it comes to FD-SOI, we have seen a lot of hype, but from our perspective, no serious production yet. Soitec says that volume is now into the thousands of wafers per month, and will hit tens of thousands by the end of the year. Some products using FD-SOI have been announced, such as the NXP (formerly Freescale) i.MX 7 and i.MX 8 series of processors. Two foundries are on board, GLOBALFOUNDRIES with their 22FDX suite of processes, and Samsung with their 28 FDSOI offering; both claim multiple tape-outs are in progress (50+ for GF), and Samsung’s Kelvin Low at Semicon West stated that they had shipped thousands of wafers. And both agree that FD-SOI is ideal for IoT, but again we have yet to see volume; so it’s a waiting game at the moment.

FD-SOI is real, though – here’s a cross-section of transistors in a Bitcoin processor chip that we looked at last year.

SFARDS2

This was fabbed by STMicroelectronics in their Crolles fab, you can see that it is gate-first HKMG with no SiGe channel used for PMOS, as in PD-SOI. The SOI layer is ~6 nm thick, so definitely FD-SOI!

Overall PD-SOI and FD-SOI, being 300-mm wafer product, make up ~20% of sales, the remaining 80% are 200-mm wafers.

70% of those 200-mm wafers are RF-SOI, which has grown steadily due to its adoption into the RF front end of mobile phones, especially in world-phones that have to cope with more than 40 wireless bands. Soitec claim that there was 18 mm2 of RF-SOI in the iPhone 6, and 25 mm2 in the iPhone 6s, and we at Chipworks/TechInsights have certainly seen increasing amounts of SOI-based parts in the RF section of the phones that we analyze. The company asserts that 100% of smartphones have their silicon in them these days.

This (together with power SOI, which we will discuss later) has kept Soitec’s 200-mm Bernin fab at full capacity for the last few months, and they expect to ship a million 200-mm wafers this year. Last year the total was 700,000 wafers, and next year they expect it to be 1.3M wafers, though some of these may be from licensees Shin-Etsu and Sun Edison. Soitec has 70% of SOI wafer sales worldwide.

Apparently there are now over ten foundries using SOI, mostly 200-mm, but Tower-Jazz has announced that its TPSCo subsidiary in Japan will be processing 45-nm, 300-mm RF-SOI, and GLOBALFOUNDRIES is now also offering 45-nm RF-SOI; I heard verbally that will be from the East Fishkill fab, but I can’t find documentary support for that at the moment.

Back at the end of 2013, Soitec announced the addition of “trap-rich” RF-SOI technology to their product line, as an enhanced performance substrate for RF products.

eSi

As I understand it, the trap-rich layer is a layer of polysilicon formed on the handle wafer, and the multiple traps in the crystal grains and grain boundaries kill any parasitic currents that could be induced by the RF radiation, even in a high-resistivity (HR) substrate. This enables “RF designers to integrate on the same chip diverse functions such as switches, power amplifiers and antenna tuners with excellent RF isolation, good insertion loss and better signal integrity than traditional technologies.”[1]

eSi2

I was curious to see what the penetration of this new technology was into RF product lines, and was surprised when Tom told me it was 55%, and it had replaced most of the regular HRSOI wafers that they had been selling, even with a 25% cost mark-up (presumably the polysilicon process is VERY specific). He said that manufacturers were willing to pay the higher price because of the improved performance, and it also saves two mask layers. At the moment it’s all 200-mm wafer sales, though 300-mm wafers are available.

As an example of the leading-edge RFSOI, here’s a SEM cross-section of a Murata/Peregrine antenna switch die from one of the RF front-end modules in the iPhone 6s:

Peregrine

The SOI layer is well under 100 nm thick, but we are not into FD-SOI yet, even though some claim that RF can be integrated into FDSOI! As it’s a SEM image with oxide staining, we can’t see if there is a trap-rich layer; that would take a different stain or TEM imaging to show it up.

Moving on to Power SOI, it is now present in 50% of cars, according to the company, with ~70 mm2 used per vehicle on average. Automotive usage is the largest sector, followed by industrial, and “other”:

PowerSOI revenue 2015

The auto sector has been expanding steadily for the last decade, due to the increasing use of automotive transceivers (CAN/LIN/FlexRay, over 50% in SOI), and class-D amplifiers in infotainment systems. On the industrial front, the driving products have been AC/DC converters, motor drivers, and Power over Ethernet.

The higher voltages and harsh environment have a lot to do with SOI migrating into these spaces – junction temperatures can get up to 225°C, and the dielectric isolation of the buried oxide helps with high-voltage operation, electrostatic discharge (ESD), and electromagnetic interference (EMI) protection. And of course it is inherently radiation-hard for particulate radiation such as alpha-particles or neutrons, great for space and military applications.

In terms of the design considerations, the use of SOI eliminates parasitic latch-up, and the ability to use oxide isolation between circuit elements saves space when compared with diffused isolation in BCDMOS (bipolar-CMOS-DMOS) processes.

BCDMOS-SOI

This can give a die size reduction of 40 – 50%, depending on the design, so well worth considering even with a higher-priced start wafer.

Photonics SOI uses a different benefit of the buried oxide layer – the ability to confine photons within a silicon waveguide. In yet more of those fortunate properties of silicon, it transmits infra-red light at 1.3 – 1.6 µm, matching the wavelengths used in fibre-optic cables; and there is a large refractive index (RI) contrast between Si (n~3.5) & SiO2 (n~1.5), giving good total internal reflection to silicon waveguides on oxide.

Schematic of SOI optical waveguide

Schematic of SOI optical waveguide

The higher refractive index also means that the wavelength is shorter in silicon, so we can have much tighter turning radii than in oxide, allowing sharp bends in photonics chips. Add to that the capability of tuning the RI by tuning the doping, and manipulating the light by applying a voltage and injecting carriers to adjust the phase, and we can do photonic processing as well as the usual digital and analog electronic processing.

The main application at present seems to be photonic transceivers, both inside and outside systems, but there is plenty of R&D looking to take advantage of the potential, particularly as data rates move towards 100 Gb/sec.

SOI Photonics2a

Currently total production is only about 10,000 wafers/year, but being targeted mainly on interconnect inside and outside data centres, that is a low volume, high value part of the business. Looking to the future, Soitec expects that the growth in data as 5G arrives will push the need for photonics products, and Tom speculated that the high data rates required for 4K/8K virtual reality systems may also drive a consumer need for optical links to the headsets.

Almost four years ago Chipworks analyzed a Luxtera chip from a Molex active fibre optic cable, fabricated by Freescale (at the time, now NXP) in a 130-nm CMOS/photonic SOI process. Here’s an optical plan-view image of a pair of waveguides turning 90o:

Luxtera1-b

Wide multi-mode waveguides come in from the left, narrow down and become single-mode waveguides before they turn 90o with a radius of 30 µm and exit at the top of the image.

Here we show a TEM cross-section of the narrow part of the waveguide:

Luxtera3-c-a-ann-b

The deep STI through to the buried oxide isolates the waveguide structure, and the shallow STI in the structure confines the optical signal to the central mesa. The extra width and the outer ribs likely act to give mechanical stability and even out the stress in the central mesa, and there is a silicon nitride layer over the waveguide which acts as a silicide mask. They are in general uniformly doped, but when they become part of a Mach-Zender interferometer (MZI), a P-N diode is formed in the waveguide in order to modulate the phase of the optical signal by varying the reverse bias on the diode. Below are junction-stained SEM and scanning capacitance microscopy (SCM) cross-sections of one waveguide in a MZI. In the SEM image, the copper metallization has been etched out, but we can see the pairs of contacts to the SOI to bias the diode.

SEM and SCM cross-sections of waveguide in Mach-Zender interferometer

SEM and SCM cross-sections of waveguide in Mach-Zender interferometer

Germanium photodetectors are formed selectively on the SOI for receive and signal-monitoring functions, and a laser diode module is mounted on the die for transmit capability.

It is obvious from this example that SOI is an almost ideal material for part of the integrated photonics systems that we will need in the not-too-distant future. Unfortunately silicon is not good for generating light, and we still need the interface to cable, so photonics chips will have to be part of an integrated assembly.

Intel made it clear last year at their Data Center Day that they consider silicon photonics a key part of their “Data Center Connectivity Landscape”, from within-rack connection to across the data center itself, which can involve kilometers of interconnects:

Intel1

They also see ~50% growth in the market in the next few years:

Intel2
And it is clear from the new roadmaps (Photonic Systems Manufacturing Roadmap, and Heterogeneous Integration Technology Roadmap for Semiconductors) that technology and cost pressures are driving developments both in volume wafer manufacturing and wafer level assembly, as well as other areas such as optical through-silicon vias.

So, if we look at all the above applications, and include the predictions for FD-SOI, Soitec not only has bounced back from its travails of a few years ago, but as the main player in the SOI wafer business, it seems to have a solid future coming up.

Reference:

IEDM 2016 Has “New Twists,” Supplier Exhibits for the First Time

By Dick James, Senior Technology Analyst, Chipworks

A bit earlier than usual, the IEDM (International Electron Devices Meeting) press kit is available, and among the announcements are a couple of surprises.

The biggest practical change is the addition of an exhibit hall – up to now the conference has been almost religiously anti-commercial, to the extent that forums (fora?) sponsored by (e.g.) Applied Materials, ASM, and Synopsys have had to be held offsite in other hotels.

To quote Tibor Grasser, IEDM 2016 Exhibits Chair, “We have decided to have a supplier exhibition in conjunction with the technical program this year, as an added way to provide attendees with the knowledge and information they need to advance the state-of-the-art.”

There is an element of truth to that, since many of the papers are authored by the R&D groups from equipment companies, and having some systems on site may help cross-fertilise ideas and techniques. Of course, a contribution to conference funds in the form of space rental always helps, too.

Another change is that the submission deadline for papers has been delayed to August 10, though there’s a twist to that too – accepted papers will appear without any modification; so BEWARE, your typos and other errors will follow you into perpetuity. Still, the later date is a good thing, in previous years submissions had to be almost six months before the conference, so finalised work could be almost a year old before presentation. There is still an opportunity for late-news papers to be submitted by 12th September.

Other than those changes, the conference follows its usual timeline from December 3rd to December 7th – tutorials on the Saturday, short courses on Sunday, plenary talks Monday morning, then likely eight parallel sessions of papers, wrapping up on the Wednesday afternoon. Interspersed through this will be the Monday evening reception, Tuesday conference lunch and evening panels, and the Entrepreneurs lunch on Wednesday.

There may also be off-site gatherings or hospitality suites; Applied Materials, ASM, Synopsys, and Silvaco have sponsored them in the past.

I would go through the schedule in more detail, but handily the Solid State Technology editorial staff have done that already. Once the full program is published, I plan on drafting my usual pre-conference review sometime towards the end of November. The conference is now in its permanent location at the San Francisco Union Square Hilton, no more visits to Washington DC.

Notes from The ConFab 2016 – Day 3

Notes from Day 1 can be found here.

Notes from Day 2 can be found here.

By Dick James, Senior Technology Analyst, Chipworks

Day 3 was just a morning session, with China being the topic. Sunny Hui, SVP Worldwide Marketing for SMIC, gave (for me) a notable keynote on “Collaborate to Win in the China Market”.

Sunny started by giving some background to China’s economic and technological growth; gross domestic product (GDP), for example, has increased by 35x in the last 30 years, to $10.4 trillion, and 40% of worldwide semiconductor shipments go to China (more is spent on semiconductors than on oil!). Depending on the segment, these semiconductors go into the 70 – 90% of electronics products that are made in China and exported. And Chinese brands are becoming well known in world markets – Huawei, Haier, Lenovo and others are no longer strange names to us in North America and Europe.

Specifically referring to SMIC, we were shown a teardown (something I recognise!) of the Huawei P8 phone, with six parts fabbed by SMIC inside it.

Capture15

Huawei P8 phone teardown with SMIC-made parts highlighted

The rise in China (and elsewhere) of ubiquitous big data, driven by cloud usage and IoT, pressures users to choose the right technology node for their chips, which gave Sunny a chance to show the SMIC technology portfolio;

Capture16
Which looks like a challenging range of processes to me! (SPOCULL = SMIC Poly on Contact Ultra Low Leakage.) We were also shown some SMIC finFETs, the first that I have seen.

Capture17
They now have three 300-mm fabs (Shanghai and Beijing 1 &2), and five 200-mm fabs, with one dedicated to the MEMS, imager and 3D IC specialty platforms, and another to bumping, WLCSP and testing; and they are aware of the need for patent coverage, having filed over 12,000 patents. They claim to be the most preferred foundry among Chinese fabless companies, with revenue from them growing at a 30% CAGR over the last ten years. SMIC has also set up a joint venture with JCET (SJSemiconductor, based in Jiangyin), focusing on wafer-level packaging technology.

In the Q&A session, someone asked if FDSOI was on the roadmap – apparently, nobody is asking, though it’s possible – the focus is still on finFETs. And 28-nm HKMG is now in production.

Next up was Ed Pausa from PricewaterhouseCoopers (PWC); I thought I was an old stager in the business these days, having started in 1970, but Ed started with Fairchild in 1959! PWC recently published a report on China’s impact on the semiconductor industry (available here), and Ed went through it in considerable detail. It appears that China’s semiconductor consumption hit a new record in 2014, at 57% of the worldwide market, and it’s been over 50% for the last four years.

When it comes to revenue, China’s semiconductor industry grew by 17.5% in 2014 to a record US$$77.3bn, making up 13.4% of worldwide semiconductors. That breaks down into 22% IC design, 15% manufacturing, 26.5% package & test, and 36.5% optoelectronics, sensors and discretes.

The gap between consumption and production continues to grow, however, to $140Bn in 2014, and it is expected to keep on growing, despite well-publicised government attempts to reduce it.

As of 2014, there were 165 wafer fabs there, of which ten are 300mm. There are now reported to be more than 660 design houses, though PWC estimates that no more than 100 are actually viable fabless companies. At the packaging, assembly and test end of the spectrum, there were 120 facilities, which gave China 33% of this type of worldwide floor space, the largest share.

In 2014 SK Hynix topped the table of semiconductor revenue, followed by HiSilicon and SMIC. Only four of the top ten appear to be domestic Chinese companies, the others are all subsidiaries of foreign multinationals.

Capture18
After Ed it was my turn to speak, and the topic of my talk was “China’s Penetration into Mobiles – Real or Imaginary?”, which gave me the chance to show a few teardowns of Chinese-made phones, and do a comparison with the iPhone SE. I started with a quick look at some smartphone statistics – by coincidence ICInsights had published them a week before The ConFab;

McClean1

 

And we can see that eight out the top twelve companies are China-based. Then I did a quick run through design wins by Mediatek, Spreadtrum and HiSilicon, before getting into the teardowns.

First we looked at a Huawei Mate 8, a high-end phone targeting the same space as the Samsung Galaxy 7 and the iPhone. This has a complex bill of materials (BOM), but the lead chips are from Huawei’s subsidiary HiSilicon, including their Kirin 950 application processor fabbed in TSMC’s 16FF+ process.

Capture19

 

Then we had a value 4G device, the JXD T5 (Blaster Mini) one of the top 10 phones in the Asia-Pacific region in March. Now that we have moved down-market, it is less complex, focused on Chinese cellphone bands, and with a cheaper camera. Mediatek dominated the silicon here, but the touchscreen controller and camera were also Chinese, from Focaltech and Omnivision.

When we get to basic 2G/3G phones (a Lenovo T2 and a Lava Iris Atom), the only non-Chinese chips are the memories and the accelerometers – everything else originated from China, including the RF front end.

For comparison we then examined the Apple iPhone SE, which of course is a complex worldphone; the winners here (apart from Apple’s own designs) were Qualcomm and Texas Instruments, and in the RF front end, Qorvo and Skyworks.

In part my talk was a not-so-subtle sales pitch for our new “Inside Technology” service, which is basically a subscription portal to our database of teardowns and parts analyses – in the case of semiconductor processes, down to the atomic scale, since it includes access to TEM images and materials analyses. Since we’ve been doing it for over twenty years, that’s a lot of data!

As with many product launches, we’ve made a video – I think it’s quite impressive, but then I am a little biased, since in the case of the teardowns, I showed, it was the tool that I used to compile the design win information and the teardown BOMs for the different phones, and in the iPhone I showed that we can see that the QFE1100 envelope tracker chip was used in 67 different phones, and that there were three different versions from two different foundries.

Capture20

 

Then we had a quick look at patent landscapes for Mediatek, Huawei, and Apple, and the penultimate slide told the story that I was focused on; using ICInsights’ categorization of the types of chips in a mobile phone, Chinese-made chips are in seven of the eight categories.

In retrospect I should not have included Mediatek, since they are Taiwan-based, but that does not change the essential nature of the story, that China-designed and fabbed chips are making their way into mobile phones, especially at the value end of the market.

Capture21

 
Given my liberal use of ICInsights’ information as background for my talk, it was slightly ironic that the final keynote speaker was Bill McClean himself, of ICInsights.

Bill started out with the background that in the last decade our IC industry cycles have morphed from a capacity/capital spending driven cycle to one that is much more controlled by world GDP.

Capture22 - Copy
Then he moved on to China’s role in the IC world, echoing Ed Pausa’s comments that the IC consumption vs IC production gap is growing, and their government is making a well-funded push to reduce that gap. His slightly surprising conclusion (at least to me) is that this effort is failing.

His contention is that there is not yet a strong indigenous pure-play foundry industry, nor a strong presence in the fabless IC supplier space, since fabs there only take ~7% of the world market (and that includes foreign-owned fabs), and the fabless companies are at 10% market share.

There have been some successes – several joint venture fabs are being set up, notably with UMC, Powerchip, and GLOBALFOUNDRIES, and on the acquisition front, (e.g.) NXP has sold two divisions to JAC Capital, and Omnivision is now China-owned. On the other hand, moves to buy Micron, Fairchild, and a chunk of Western Digital have failed, and Bill’s opinion is that any significant purchases of US-based companies are now highly unlikely, and other governments are taking a similar position.

That wrapped up the Confab for this year, just a final networking lunch to finish, and then we all went our different ways. The ConFab in 2017 will be on June 14 – 17, again at the Encore in Las Vegas.