Tag Archives: cost

Moore’s Law Smells Funny

…maybe we need “Integrated Cleverness Law”

“Jazz is not dead, it just smells funny.” – Frank Zappa 1973
from Be-Bop Tango (Of The Old Jazzmen’s Church)

Marketing is about managing expectations. IC marketing must position next-generation chips as adding significant new/improved functionalities, and for over 50 years the IC fab industry has leaned on the conceptual crutch of “so-called Moore’s Law” (as Gordon Moore always refers to it) to do so. For 40 years the raw device count was a good proxy for a better IC, but since the end of Dennard Scaling the raw transistor count on a chip is no longer the primary determinant of value.

Intel’s has recently released official positions on Moore’s Law, and the main position is certainly correct:  “Advances in Semi Manufacturing Continue to Make Products Better and More Affordable,” as per the sub-headline of the blog post by Stacy Smith, executive vice president leading manufacturing, operations, and sales for Intel. Smith adds that “We have seen that it won’t end from lack of benefits, and that progress won’t be choked off by economics.” This is what has been meant by “Moore’s Law” all along.

When I interviewed Gordon Moore about all of this 20 years ago (“The Return of Cleverness” Solid State Technology, July 1997, 359), he wisely reminded us that before the industry reaches the limits of physical scaling we will be working with billions of transistors in a square centimeter of silicon. There are no ends to the possibilities of cleverly combining billions of transistors with sensors and communications technologies to add more value to our world. Intel’s recent spend of US$15B to acquire MobileEye is based on a plan to cost-effective integrate novel functionalities, not to merely make the most dense IC.

EETimes reports that at the International Symposium on Physical Design (ISPD 2017) Intel described more than a dozen technologies it is developing with universities and the SRC to transcend the limitations of CMOS. Ian Young, a senior fellow with Intel’s Technology Manufacturing Group and director of exploratory integrated circuits in components research, recently became the editor-in-chief of a new technical journal called the IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, which explores these new CMOS-fab compatible processes.

Meanwhile, Intel’s Mark Bohr does an admirable job of advocating for reason when discussing the size of minimally scaled ICs. Bohr is completely correct in touting Intel’s hard-won lead in making devices smaller, and the company’s fab prowess remains unparalleled.

As I posted here three years ago in my “Moore’s Law Is Dead” blog series, our industry would be better served by retiring the now-obsolete simplification that more = better. As Moore himself says, cleverness in design and manufacturing will always allow us to make more valuable ICs. Maybe it is time to retire “Moore’s Law” and begin leveraging a term like “Integrated Cleverness Law” when telling the world that the next generation of ICs will be better.


Thermoplastically Deformable Electronic Circuits

Philips is testing a technology developed by imec and CMST (imec’s associated lab at Ghent University) to create low-cost 3D LED packages. As shown at last month’s International Microelectronics Assembly and Packaging Society (IMAPS 2015) meeting, these thermoplastically deformable electronic circuits are already being integrated by Philips into LED lamp carriers, a downlight luminaire, and a omnidirectional light source.

Miniature dome test vehicle with integrated low power LEDs, (a) circuit before forming, and (b) circuit after vacuum forming using a 40mm half-sphere mold. (Source: imec)

Miniature dome test vehicle with integrated low power LEDs, (a) circuit before forming, and (b) circuit after vacuum forming using a 40mm half-sphere mold. (Source: imec)

The technology is based on meander-shaped interconnects, which are patterned using  standard printed circuit board (PCB) production equipment and then sandwiched between 2D thermoplastic polymer (e.g. polycarbonate) sheets. The Figure shows one example in final form after vacuum thermoforming into a 40mm half-sphere mold.
This is a glorious example of “elegant engineering” where a clever combination of materials and processes has been integrated with highly desirable characteristics:  low tooling cost, low direct material cost, easily scalable from lab to fab, low product weight, and high product resilience. This seems to represent almost a new industrial product category that combines a “package” and a PCB.



EUV Cost at 1000 Daily Exposures

On October 14, 2015, ASML Holding N.V. (ASML) published its 2015 third-quarter results:  Q3 net sales of €1.55 billion with gross margin of 45.4% (in line with guidance), and guided Q4 2015 net sales at approximately €1.4 billion and a gross margin of around 45%. Due to mismatched financial analyst expectations, Bloomberg reported that ASML’s stock price dropped ~7% in a single day of trading, despite the company also reporting upgrades to both the TWINSCAN NXT 193nm-immersion (193i) and the NXE Extreme Ultraviolet (EUV) tools. In particular, a new record of 1000 wafer exposures in a single day was set by one EUV tool.

The science of controlling the 13.54nm wavelength electromagnetic radiation that we like to call “Extreme Ultra-Violet” or “EUV” (instead of the colloquial scientific term “soft x-ray”) is inherently challenging. The engineering of EUV Lithography is not just challenging but bordering on inherently impossible:  from exploding tin plasma source, to all-reflective lenses that absorb energy, to the trade-offs in mask pattern protection. The team at ASML working on the exposure tool—along with the different specialist organizations still working on improved sources, masks, and resists—deserve the industry’s unwavering admiration for the important work they do every day.

In a prepared statement, ASML President and Chief Executive Officer Peter Wennink said, “We have proven the capability both to expose 1,000 wafers per day and, in a manufacturing readiness test, to expose 15,000 wafers in four weeks. We have also achieved a four-week average availability of more than 70 percent  at multiple customer sites. The first shipment of our fourth-generation EUV lithography system, the NXE 3350B, is in progress, with two more expected to ship in Q4.”

Still, progress along desired EUV roadmaps continues to be slow, and the competitive target shifts when the 193i exposure tool gains a 10% throughput improvement to 275 wafer-passes/hour (wph). When the 193i tool gains a 30% overlay improvement, that means double-patterning based on litho-etch-litho-etch (LELE) process flows gain in pattern fidelity. Since ASML provides both technologies, delays in orders for EUV just means more sales of 193i tools.

Let’s play with the numbers here…275 wph x 20 hours x 30 days = 165k wafer-passes/month for the NXT:1980. The NXE:3350B can current handle 15k wafer-passes/month. So even if the tools were equally priced, just based on tool depreciation each EUV exposure today costs >10x that of a 193i exposure, which is why pitch-splitting multi-patterning 193i continues to dominate.


Leti Shows MEMS on 300mm Wafers

As reported by EETimes from the European MEMS Summit last month, French research institute CEA-Leti has manufactured accelerometer MEMS devices on 300mm-diameter wafers. This technology is currently being transferred to Tronics Microsystems SA (Grenoble, France), which currently only manufactures on 200mm wafers. Since CEA-Leti has long functioned as the R&D group for STMicroelectronics (ST), and previously led the way for ST to produce MEMS chips on 200mm-diameter wafers, we may expect that 300mm-wafer MEMS processing is now on ST’s internal roadmap.
Moving production to larger wafers makes sense when either the chip-size or the manufacturing volume increase in size. Much of the growth in demand for MEMS is for so-called “combo” sensors that combine multiple sensor technologies, such as CEA-Leti’s piezo-resistive silicon nanowire technology which allows the accelerometer, gyroscope, magnetometer, and pressure sensor capability to be integrated on the same chip.
The compatibility of Leti’s 200mm-developed technologies with 300mm wafer fabrication, “shows a significant opportunity to cut MEMS production costs,” said Leti CEO Marie Semeria in a press release. “This will be especially important with the worldwide expansion of the Internet of Things and continued growing demand for MEMS in mobile devices.” Sensors of all sorts will be needed for all of the different “Things” to be able to capture new useful information, so we may expect that demand for combo MEMS devices will continue to increase.

CMP Slurry Trade-offs in R&D

As covered at SemiMD.com, the CMP Users Group (of the Northern California Chapter of The American Vacuum Society) recently held a meeting in Albany, New York in collaboration with CNSE, SUNY Polytechnic Institute, and SEMATECH. Among the presentations were deep dives into the inherent challenges of CMP slurry R&D.
Daniel Dickmann of Ferro Corporation discussed trade-offs in designing CMP slurries in his presentation, “Advances in Ceria Slurries to Address Challenges in Fabricating Next Generation Devices.” Adding H2O2 to ceria slurry dramatically alters the zeta-potential of the particles and thereby alters the removal rates and selectivities. For CMP of Shallow Trench Isolation (STI) structures, adding H2O2 to the slurry allows for lowering of the particle concentration from 4% to <2% while maintaining the same removal rate. Reducing the average ceria particle size from 130nm to 70nm results in a reduction in scratch defects while maintaining the same removal rate by tuning the chemistry, but the company has not yet found chemistries that allow for reasonable removal rates with 40nm diameter particles. The ceria morphology is another variable that must be controlled according to Dickmann, “It can seem counter-intuitive, but we’ve seen that non-spherical particles can demonstrate superior removal-rates and defectivities compared to more perfect spheres.”
Selectivity is one of the most critical and difficult aspects of the CMP process, and arguably the key distinction between CMP and mere polishing. The more similarity between the two or more exposed materials, the more difficult to design high selectivity in a slurry. Generally, dielectric:dielectric selectivity is difficult, and how to develop a slurry that is highly selective to nitride (Si3N4) instead of TEOS-oxide (PECVD SiO2 using tetra-ethyl-ortho-silicate precursor) was discussed by Takeda-san of Fujimi Corporation. In general, dielectric CMP is dominated by mechanical forces, so the slurry chemistry must be tuned to achieve selectivity. Choosing <5 pH for the slurry allows for reducing the oxide removal rate while maintaining the rate of nitride removal. Legacy nitride slurries have acceptable selectivities but unacceptable edge-over-erosion (EOE) – the localized over-planarization often seen near pattern edges. Reducing the particle size reduces the mechanical force across the surface such that chemical forces dominate the removal even more, while EOE can be reduced because negatively charged particles are attracted to the positively charged nitride surface resulting in local accumulation.