Tag Archives: heterogeneous

The Last Technology Roadmap

After many delays, the last ever International Technology Roadmap for Semiconductors (ITRS) has been published. Now that there are just a few companies remaining in the world developing new fab technologies in each of the CMOS logic and memory spaces, each leading-edge company has a secret internal roadmap and little motivation to compare directions within fiercely competitive  commercial markets. Solid State Technology Chief Editor Pete Singer covered these developments in his blog post early last year.

Rachael Courtland at IEEE Spectrum provides a great overview of the topic and interviews many of the key contributors to this last global effort. The article provides a nice graph to show how the previously predicted (in the just-prior ITRS 2013 edition) continued physical gate length reduction of CMOS transistors is now expected to stop in 2020. Henceforth, 3D stacking of transistors—perhaps built with arrays of Gate-All-Around NanoWires (GAA-NW)—will be the only way to get more density in circuitry but it will come with proportionally increasing cost.

As Gary Patton, CTO and SVP of Worldwide R&D for GlobalFoundries, mentioned during the 2016 Imec Technology Forum in Brussells, “We will continue to provide value to our customers to be able to create new products. We’re going to innovate to add value other than simple scaling.”

The 17 International Technology Working Groups (ITWGs) were replaced in 2015 by 7 Focus Teams in the last ITRS:  System Integration, Heterogeneous Integration, Heterogeneous Components, Outside System Connectivity, More Moore, Beyond CMOS and Factory Integration. The final reports from each Focus Team are available for free download from Dropbox.

The IEEE Rebooting Computing Initiative, Standards Association, and the Computer Society announced a new International Roadmap for Devices and Systems (IRDS) on 4th of May this year. Paolo Gargini is leading this work that began with the partnership between the IEEE RC initiative and the ITRS, with aspiration to build “a comprehensive end-to-end view of the computing ecosystem, including devices, components, systems, architecture, and software.”

In parallel to the IRDS efforts, the Heterogeneous Integration Roadmap activities will continue as sponsored by IEEE Components, Packaging and Manufacturing Technology Society (CPMT), SEMI  and the IEEE Electron Devices Society (EDS). Bill Bottoms is leading this collaboration with other IEEE Technical Societies that share interest in the Heterogeneous Technology Roadmap as well as to organizations outside IEEE that share this common vision for the roadmap.


IBM Shows Graphene as Epi Template

Last month in Nature Communications (doi:10.1038/ncomms5836) IBM researchers Jeehwan Kim, et al. published “Principle of direct van der Waals epitaxy of single-crystalline films on epitaxial graphene.” They show the ability to grow sheets of graphene on the surface of 100mm-diameter SiC wafers, the further abilitity to grow epitaxial single-crystalline films such as 2.5-μm-thick GaN on the graphene, the even greater ability to then transfer the grown GaN film to any arbitrary substrate, and the complete proof-of-manufacturing-concept of using this to make blue LEDs.

(Source: IBM)

(Source: IBM)

The figure above shows the basic process flow. The graphenized-SiC wafer can be re-used to grow additional transferrable epi layers. This could certainly lead to competition for the Leti/Soitec/ST “SmartCut” approach to layer-transfer using hydrogen implants into epi layers.
No mention is made of the kinetics of growing 100mm-diameter sheets of single-crystalline GaN on graphene. Supplemental information in the online article mentions 1 hour at 1250°C to cover the full wafer, but the thickness grown in that time is not mentioned. From first principles of materials engineering, they must either:

A) Go slow at first to avoid independent islands growing to form a multicrystalline layer, or
B) Initially grow a multicrystalline layer and then zone anneal (perhaps using a scanned laser) to transform it into a single-crystal.
In either case, we would expect that after just a few single-crystalline atomic layers had been either slowly grown or annealed, that a 2nd much-higher speed epi process would be used to grow the remain microns of material. More details can be seen in the EETimes write up.