Tag Archives: ITRS

The Last Technology Roadmap

After many delays, the last ever International Technology Roadmap for Semiconductors (ITRS) has been published. Now that there are just a few companies remaining in the world developing new fab technologies in each of the CMOS logic and memory spaces, each leading-edge company has a secret internal roadmap and little motivation to compare directions within fiercely competitive  commercial markets. Solid State Technology Chief Editor Pete Singer covered these developments in his blog post early last year.

Rachael Courtland at IEEE Spectrum provides a great overview of the topic and interviews many of the key contributors to this last global effort. The article provides a nice graph to show how the previously predicted (in the just-prior ITRS 2013 edition) continued physical gate length reduction of CMOS transistors is now expected to stop in 2020. Henceforth, 3D stacking of transistors—perhaps built with arrays of Gate-All-Around NanoWires (GAA-NW)—will be the only way to get more density in circuitry but it will come with proportionally increasing cost.

As Gary Patton, CTO and SVP of Worldwide R&D for GlobalFoundries, mentioned during the 2016 Imec Technology Forum in Brussells, “We will continue to provide value to our customers to be able to create new products. We’re going to innovate to add value other than simple scaling.”

The 17 International Technology Working Groups (ITWGs) were replaced in 2015 by 7 Focus Teams in the last ITRS:  System Integration, Heterogeneous Integration, Heterogeneous Components, Outside System Connectivity, More Moore, Beyond CMOS and Factory Integration. The final reports from each Focus Team are available for free download from Dropbox.

The IEEE Rebooting Computing Initiative, Standards Association, and the Computer Society announced a new International Roadmap for Devices and Systems (IRDS) on 4th of May this year. Paolo Gargini is leading this work that began with the partnership between the IEEE RC initiative and the ITRS, with aspiration to build “a comprehensive end-to-end view of the computing ecosystem, including devices, components, systems, architecture, and software.”

In parallel to the IRDS efforts, the Heterogeneous Integration Roadmap activities will continue as sponsored by IEEE Components, Packaging and Manufacturing Technology Society (CPMT), SEMI  and the IEEE Electron Devices Society (EDS). Bill Bottoms is leading this collaboration with other IEEE Technical Societies that share interest in the Heterogeneous Technology Roadmap as well as to organizations outside IEEE that share this common vision for the roadmap.


Chasing IC Yield when Every Atom Counts

Increasing fab costs coming for inspection and metrology
ITRS2013_Yield_overviewAt SEMICON West this year in Thursday morning’s Yield Breakfast sponsored by Entegris, top executives from Qualcomm, GlobalFoundries, and Applied Materials discussed the challenges to achieving profitable fab yield for atomic-scale devices (Figure source is the ITRS 2013 Yield Chapter). Due to the sensitive nature of the topic, recording was not allowed and copies of the presentations could not be shared.
Qualcomm – Geoffrey Yu
Double-patterning will be needed for metal and via layers as we go before 90nm pitch for the next generations of ICs. Qualcomm is committed to designing IC with smaller features, but not all companies may need to do so. Fab costs keep going up for atomic-scale devices…and there are tough trade-offs that must be made, including possibly relaxing reliability requirements. “Depending on the region. If you’re in an emerging region maybe the reliability requirements won’t be as high,” said Yu. Through-Silicon Vias (TSV) will eventually be used to stack IC layers, but they add cost and will only be used when performance cannot be met with cheaper solutions. “An early idea was to use TSV for logic:memory,” reminded Yu, “but then there was innovation to LPDDR4 allowing it deliver the same bandwidth with one-half the power of LPDDR3, which delayed TSV.”
GlobalFoundries – Harry Levenson
“A more expensive part could provide a better value proposition for a customer,” reminded Levenson as he discussed the challenges of inspecting next-generation commercial ICs in high-volume manufacturing (HVM). “We still have clear demand for products to run in HVM at the leading edge, but we are now in the world of double-patterning and this applies to optical inspection as well as imaging.” Requirements for inspection and imaging are different, but he same physics applies. In imaging Depth of Focus (DoF) of ~140nm is generally preferred, while the same used for inspection  of a <140nm thin film would to induce noise from lower-levels. We can’t do e-beam inspections due to too much energy concentration needed to get acceptable throughput (and the challenge gets worse as the pixel area is reduced, inherently slowing down throughput). However, e-beams are helpful because they can detect open contracts/vias in metal levels due to the conductivity of electrons providing additional contrast compared to any possible optical inspection.
Applied Materials – Sanjiv Mittal
Mittal discussed how the CMOS transistor gate formation process has increased in complexity over the last few device generations:  8x more unit-process steps, 3x higher fab cost, 50x lower defects needed for yield. “The challenges are immense,” admitted Mittal. “What happens when you try to work on yield improvement when you’re ramping volume? At the same time you’re trying to improve yield by making changes, you’re trying to increase the volume by not making changes.”
Entegris – Jim O’Neill
O’Neill is CTO of the combined Entegris post-merger with ATMI, and was recently director of advanced process R&D for IBM. Since Entegris provides materials and sub-systems, in the simplest cases the company works to improve IC fab yield by minimizing defects. “However, the role of the materials-supplier should change,” averred O’Neill. “The industry needs bottle-to-nozzle wet chemistry solutions, and applications-based clean gas delivery.” In an exclusive interview with SST/SemiMD, O’Neill provided as example of a ‘wetted process solution’ a post-CMP-clean optimized through tuning of the brush polymer composition with the cleaning chemistry.
ITRS Difficult Challenges for Yield 2013-2020

  • Existing techniques trade-off throughput for sensitivity, but at expected defect levels, both throughput and sensitivity are necessary for statistical validity.
  • Reduction of inspection costs and increase of throughput is crucial in view of CoO.
  • Detection of line roughness due to process variation.
  • Electrical and physical failure analysis for killer defects at high capture rate, high throughput and high precision.
  • Reduction of background noise from detection units and samples to improve the sensitivity of systems.
  • Improvement of signal to noise ratio to delineate defect from process variation.
  • Where does process variation stop and defect start?