Tag Archives: lithography

EUVL Masks may need to be Tool-Specific

Extreme Ultra-Violet Lithography (EUVL) keeps hurting my brain. Just when I can understand how it could be used in profitable commercial high-volume manufacturing (HVM) I hear something that seriously strains my brain. First it was the mirrors and mask in vacuum, then it was the resist and pellicle, then it was the source power and availability, and in each case scientists and engineers did amazing work and showed a way to HVM. Now we hear that EUVL might require fabs to park work-in-progress (WIP) lots of wafers behind a single critical tool with an idealistic 80% availability on a good day, and lots of downtime bad days. Horrors!

For “5nm-node” designs the maximum allowable edge placement-error (EPE) in patterning overlay is only 2nm. While the physics of ~13.5nm wavelength EUVL means that aberration in the reflecting mirrors appears as up to 3nm variation in the fidelity of projected patterns. This variation can be measured and compensated for at the physical mask level, but then each mask would only be good for one specific exposure tool. John Sturtevant—SPIE Fellow, and director of RET product development in the Design to Silicon Division at Mentor Graphics—briefly discussed this on February 26th during Nikon LithoVision held just before SPIE Advanced Lithography.

Sturtevant explained that the Zernike coefficients for EUV are inherently almost 1 order-of-magnitude higher than for DUV at 193nm wavelength, as detailed in the SemiMD article “Edge Placement Error Control in Multi-Patterning.” How the inherent physical sources of aberration must be tightened to avoid image distortion and contrast loss as they scale with wavelength was discussed by by Fenger et al. in 2013 in the article “Extreme ultraviolet lithography resist-based aberration metrology” (doi:10.1117/1.JMM.12.4.043001).

—E.K.

Flagello to receive Zernike Award at SPIE Advanced Lithography

Flagello-DonisDonis Flagello, president, CEO, and COO of Nikon Research Corporation of America (NRCA), will be presented with the 2017 Frits Zernike Award for Microlithography on Monday 27 February during SPIE Advanced Lithography in San Jose, California. The award, presented annually for outstanding accomplishments in microlithography technology, recognizes Flagello’s leading role in understanding and improving image formation in optical lithography for semiconductor manufacturing.

A prominent member of the industry since the early 1980s and a longtime SPIE Fellow, Flagello has primarily focused on the rigorous application of physics to lithography modeling and problem solving. Early in his career, while at IBM T.J. Watson Research Center, he developed the first practical test for measuring flare in optical lithography tools and made major contributions to high numerical aperture (NA) modeling including vector and polarization effects, and radiometric correction. At ASML he played an important role in providing analysis of aberrations for new systems and high-NA imaging effects due to polarization.

Another notable aspect of his career, Flagello’s presentations at lithography conferences and papers in various journals have inspired a better understanding of optics and resist behavior and helped drive optical lithography forward, colleagues said. “His presentations are known for their combination of humor with a deep understanding of the complex interactions between physical optics and lithographic process technology,” said David Williamson, an NRCA Fellow and previous Frits Zernike Award winner. “His combined theoretical and practical production experience and knowledge are rare in this field.”

—E.K.

Patterning with Films and Chemicals

Somewhere around 40nm is the limit on the smallest half-pitch feature that can be formed with a single-exposure of 193-nm wavelength laser light using water immersion (193i) lithography. While multiple-patterning (MP) is needed to achieve tighter half-pitches, smaller features at the same pitch can be formed using technology extensions of 193i. “Chemistry is key player in lithography process,” is the title of a short video presentation by Dow Electronic Materials corporate fellow Peter Trefonas now hosted on the SPIE website (DOI: 10.1117/2.201608.02).

Trefonas as been working on chemistries for lithography for decades, including photoresists, antireflectant coatings, underlayers, developers, ancillary products, and environmentally safer green products. He is an inventor on 61 US patents, has over 25 additional published active U.S. patent applications, is an author of 99 journal and technical publications, and is a recipient of the 2014 ACS Heroes of Chemistry Award and the 2013 SPIE C. Grant Willson Best Paper Award in Patterning Materials and Processes. Now a Senior Member of SPIE, he earned his Ph.D. in inorganic chemistry with Prof. Robert West at the University of Wisconsin-Madison in 1985.

Trefonas explains how traditional Chemically-Amplified (CA) resists are engineered with Photo-Acid Generators (PAG) to balance the properties for advanced lithography. However, in recent years the ~40-nm half-pitch resolution limit has been extended with chemistries to shrink contact holes, smooth line-width roughness, and to do frequency-multiplication using Directed Self-Assembly (DSA). All of these resolution extension technologies rely upon chemistry to create the final desired pattern fidelity.

—E.K.

Trefonas Earns 2016 Perkin Medal

The Society of Chemical Industry (SCI), America Group, announced on May 5, 2016 that Peter Trefonas, Ph.D., corporate fellow in Electronic Materials at Dow Chemical Co (NYSE:DOW), has won the 2016 SCI Perkin Medal. This honor recognizes Trefonas’ contributions in the development of chemicals that enable microlithography for the fabrication of microelectronic circuits. Trefonas will receive the medal at a dinner in his honor on Tuesday, September 13, 2016, at the Hilton Penn’s Landing Hotel in Philadelphia.

TrefonasTrefonas made major contributions to the development of many successful products which are used in the production of integrated circuits spanning device design generations from 2 microns to 14 nanometers. These include photoresists, antireflectant coatings, underlayers, developers, and ancillary products. At the most recent SPIE Advanced Lithography conference he was part of a team that presented on the use of a resolution extension material, “Chemical trimming overcoat: an enhancing composition and process for 193nm lithography.”

He is an inventor on 61 US patents, has over 25 additional published active U.S. patent applications, is an author of 99 journal and technical publications, and is a recent recipient of both the 2014 ACS Heroes of Chemistry Award and the 2014 SPIE Willson Award. His research career began at Monsanto, and moved via acquisitions by Shipley, Rohm&Haas, and Dow.

—E.K.

SAQP Specs for 7nm finFETs

As discussed in my last Ed’s Threads, lithography has become patterning as evidenced by first use of Self-Aligned Quadruple Patterning (SAQP) in High Volume Manufacturing (HVM) of memory chips. Meanwhile, industry R&D hub imec has been investigating use of SAQP for “7nm” and “5nm” node finFET HVM, as reported as SPIE-AL this year in Paper 9782-12.
The specifications for pitches ranging from 18 to 24 nanometers are as follow:

  • 7.0nm Critical Dimension (CD) after etch,
  • 0.5nm (3sigma) CD uniformity (CDU), and
  • <1nm Line-Width and Line-End Roughness (LWR and LER) assuming 10% of CD.

“Pitch walk”—variation in final pitch after multi-patterning—results in different line widths, and can result in subsequent excessive etch variation due to non-uniform loading effects. To keep the pitch walk in SAQP at acceptable levels for the 7nm node, the core-1 CDU has to be 0.5nm 3sigma and 0.8nm range after both litho and etch. In other presentations at SPIE-AL this year, the best LER after litho was ~4nm, improving to ~2nm after PEALD smoothing of sidewalls, but still double the desired spec.

The team at imec developed a SAQP flow using amorphous-Carbon (aC) and amorphous-Silicon (aSi) as the cores, and low-temperature Plasma-Enhanced Atomic-Layer Deposition (PEALD) of SiO2 for both sets of spacers. Bilayer DARC (SiOC) and BARC were used for reflectivity control. Compared to SAQP schemes where the mandrels are only aSi, imec claims that this approach saves 20% in cost due to the use of aC core and the elimination of etch-stopping-layers.

—E.K.

Litho becomes Patterning

Once upon a time, lithographic (litho) processes were all that IC fabs needed to transfer the design-intent into silicon chips. Over the last 10-15 years, however, IC device structural features have continued to shrink below half the wavelength of the laser light used in litho tools, such that additional process steps are needed to form the desired features. Self-Aligned Double Patterning (SADP) schemes use precise coatings deposited as “spacers” on the sidewalls of mandrels made from developed photoresist or a sacrificial material at a given pitch, such that after selective mandrel etching the spacers pitch-split. SADP has been used in HVM IC fabs for many years now. Self-Aligned Quadruple Pattering (SAQP) has reportedly been deployed in a memory IC fab, too.

An excellent overview of the patterning complexities of SAQP was provided by Sophie Thibaut of TEL in a presentation at SPIE-AL on “SAQP integration using spacer on spacer pitch splitting at the resist level for sub-32nm pitch applications.” Use of a spacer-on-spacer process flow—enabled by clever combinations of SiO2 and TiO2 spacers deposited by Atomic Layer Deposition (ALD)—requires the following unit-process steps:
1 193i litho,
2 ALD spacers,
2 wet etches, and
4 plasma etches.

Since non-litho processes dominate the transfer of design-intent to silicon, from first principles we should consider such integrated flows as “patterning.” Etch selectivity to remove one material while leaving another, and deposition dependent on underlying materials determine much of the pattern fidelity. Such process flows are new to IC fabs, but have been used for decades in the manufacturing of Micro-Electrical Mechanical Systems (MEMS), though generally on a patterning length scale of microns instead of the nanometers needed for advanced ICs. R&D labs today are even experimenting with Self-Aligned Octuple Patterning (SAOP), and based on the legacy of MEMS processing it certainly could be done.

—E.K.

EUV Cost at 1000 Daily Exposures

On October 14, 2015, ASML Holding N.V. (ASML) published its 2015 third-quarter results:  Q3 net sales of €1.55 billion with gross margin of 45.4% (in line with guidance), and guided Q4 2015 net sales at approximately €1.4 billion and a gross margin of around 45%. Due to mismatched financial analyst expectations, Bloomberg reported that ASML’s stock price dropped ~7% in a single day of trading, despite the company also reporting upgrades to both the TWINSCAN NXT 193nm-immersion (193i) and the NXE Extreme Ultraviolet (EUV) tools. In particular, a new record of 1000 wafer exposures in a single day was set by one EUV tool.

The science of controlling the 13.54nm wavelength electromagnetic radiation that we like to call “Extreme Ultra-Violet” or “EUV” (instead of the colloquial scientific term “soft x-ray”) is inherently challenging. The engineering of EUV Lithography is not just challenging but bordering on inherently impossible:  from exploding tin plasma source, to all-reflective lenses that absorb energy, to the trade-offs in mask pattern protection. The team at ASML working on the exposure tool—along with the different specialist organizations still working on improved sources, masks, and resists—deserve the industry’s unwavering admiration for the important work they do every day.

In a prepared statement, ASML President and Chief Executive Officer Peter Wennink said, “We have proven the capability both to expose 1,000 wafers per day and, in a manufacturing readiness test, to expose 15,000 wafers in four weeks. We have also achieved a four-week average availability of more than 70 percent  at multiple customer sites. The first shipment of our fourth-generation EUV lithography system, the NXE 3350B, is in progress, with two more expected to ship in Q4.”

Still, progress along desired EUV roadmaps continues to be slow, and the competitive target shifts when the 193i exposure tool gains a 10% throughput improvement to 275 wafer-passes/hour (wph). When the 193i tool gains a 30% overlay improvement, that means double-patterning based on litho-etch-litho-etch (LELE) process flows gain in pattern fidelity. Since ASML provides both technologies, delays in orders for EUV just means more sales of 193i tools.

Let’s play with the numbers here…275 wph x 20 hours x 30 days = 165k wafer-passes/month for the NXT:1980. The NXE:3350B can current handle 15k wafer-passes/month. So even if the tools were equally priced, just based on tool depreciation each EUV exposure today costs >10x that of a 193i exposure, which is why pitch-splitting multi-patterning 193i continues to dominate.

—E.K.