Tag Archives: R&D

Mott Memristor Chaos could make Efficient AI

Congratulations to Suhas Kumar, John Paul Strachan, and R. Stanley Williams of Hewlett Packard Labs in Palo Alto for showing not just how to make a Mott memristor, but that you can create controlled chaos with one. “We showed that this type of memristor can generate chaotic and nonchaotic signals,” says Williams, who invented the memristor based on theory by Leon Chua. An analysis of the material science and engineering of titanium sub-oxides as practiced by Williams at HPL for the production of standard memristors can be found in one of my old blog posts (http://www.betasights.net/wordpress/?p=1006).

Cross-section TEM of a Mott memristor composed of 8nm niobium dioxide layer between top layer of titanium nitride and bottom pillar of titanium nitride. (Original Image: Suhas Kumar/Hewlett Packard Labs, color commentary by Ed Korczynski)

Cross-section TEM of a Mott memristor composed of 8nm niobium dioxide layer between top layer of titanium nitride and bottom pillar of titanium nitride. (Original Image: Suhas Kumar/Hewlett Packard Labs, color commentary by Ed Korczynski)

The Figure shows a cross-section of a single Mott memristors formed by the region of the 8nm thin niobium dioxide (NbO2) layer that is between the 70nm diameter titanium-nitride (TiN) pillar functioning as bottom electrode and the blanket TiN layer functioning as top electrode.

Such a device exhibits both current-controlled and temperature-controlled (https://en.wikipedia.org/wiki/Mott_transition) negative differential resistance, and the proper choice of current and temperature can result in what I like to term “repeatable” chaos. It is repeatable in that a state can be controlably placed into or out-of chaos using non-linearities in electrical current-flow and temperature. From the abstract of the original article in Nature:

We incorporate these memristors into a relaxation oscillator and observe a tunable range of periodic and chaotic self-oscillations. We show that the nonlinear current transport coupled with thermal fluctuations at the nanoscale generates chaotic oscillations. Such memristors could be useful in certain types of neural-inspired computation by introducing a pseudo-random signal that prevents global synchronization and could also assist in finding a global minimum during a constrained search.

In a simulated circuit, an array of Mott memristors can be integrated with standard memristors to form a simulated Hopfield network (https://en.wikipedia.org/wiki/Hopfield_network). Hopfield nets seem to be some of the most apt models for human memory, so if we can just wire together a sufficient number of NbO Mott memristors with TiO standard memristors then we might be a step closer to functional AI.

Read the fine coverage at IEEE Spectrum:  https://spectrum.ieee.org/nanoclast/semiconductors/devices/memristordriven-analog-compute-engine-would-use-chaos-to-compute-efficiently

Or the Nature article behind paywall:  https://www.nature.com/nature/journal/v548/n7667/full/nature23307.html


PCM + ReRAM = OUM as XPoint

The good people at TECHINSIGHTS have reverse-engineered an Intel “Optane” SSD to cross-section the XPoint cells within (http://www.eetimes.com/author.asp?section_id=36&doc_id=1331865&), so we have confirmation that the devices use chalcogenide glasses for both the switching layer and the selector diode. That the latter is labeled “OTS” (for Ovonic Threshold Switch) explains the confusion over the last year as to whether this device is a Phase-Change Memory (PCM) or Resistive Random Access Memory (ReRAM)…it seems to be the special variant of ReRAM using PCM material that has been branded Ovonic Unified Memory or “OUM” (https://www.researchgate.net/publication/260107322_Programming_Speed_in_Ovonic_Unified_Memory).

As a reminder, cross-bar ReRAM devices function by voltage-driven pulses creating resistance changes in some material. The cross-bars allow for reading and writing all the bits in a word-string in a manner similar to Flash arrays.

In complete contrast, Phase Change Memory (PCM) cells—as per the name—rely upon the change between crystalline and amorphous material phases to alter resistance. The standard way to change phases is with thermal energy from an integrated set of heater elements. The standard PCM architecture also requires one transistor for each memory cell in a manner similar to DRAM arrays.

Then we have the OUM variant of PCM as previously branded by Energy Conversion Devices (ECD) and affiliated shell-campanies founded by tap-dancer-extraordinaire Stanford Ovshinsky (https://en.wikipedia.org/wiki/Stanford_R._Ovshinsky). So-called “Ovonic” PCM cells see phase-changes driven by voltage pulses without separate heater elements, such that from a circuit architecture perspective they are cross-bar ReRAMs.

Ovshinsky et al. successfully sold this technology to industry many times. In 2000, it was licensed to STMicroelectronics. Also in 2000, it was used to launch Ovonyx with Intel investment (http://www.eetimes.com/document.asp?doc_id=1176621), at which time Intel said the technology would take a long time to commercialize. In 2005 Intel re-invested (http://www.businesswire.com/news/home/20051019005145/en/Ovonyx-Receives-Additional-Investment-Intel-Capital). Finally in 2009, Intel and Numonyx showed a functional 64Mb XPoint test chip at IEDM (http://www.eetimes.com/document.asp?doc_id=1176621).

In 2007, Ovonxyx licensed it to Hynix (http://www.eetimes.com/document.asp?doc_id=1167173), and Qimonda (https://www.design-reuse.com/news/15022/ovonyx-qimonda-sign-technology-licensing-agreement-phase-change-memory.html), and others. All of those license obligations were absorbed by Micron when acquiring Ovonyx (https://seekingalpha.com/article/3774746-micron-tainted-love). ECD is still in bankruptcy (http://www.kccllc.net/ecd/document/list/3153).

So, years of R&D and JVs are behind the XPoint Optane(TM) SSDs. They are cross-bar architecture ReRAM arrays of PCM materials, and had the term not been ruined by 17-years of over-promising and under-delivering they would likely have been called OUM chips. Many others tried and failed, but Intel/Micron finally figured out how to make commercial gigabit-scale cross-bar NVMs using OUM arrays. Now they just have to yield the profits…


MEMS Mirrors for LIDAR

Clever integration of new microelectronic/nanoelectronic technologies will continue to provide increased functionalities for modern products. Light Imaging, Detection, And Ranging (LIDAR) technology uses lasers to see though fog and darkness, and smaller less expensive LIDAR systems are needed for autonomous driving applications now being developed by dozens of major companies around the world. A significant step in the right direction has been taken by the US government’s Lawrence Livermore National Laboratory (LLNL) after working with AMFitzgerald on a MEMS mirror Light-field Directing Array (LDA) prototype.

In-process photo of the Light-field Directing Array (LDA) MEMS prototype designed by Lawrence Livermore National Laboratory. (Source: AMFitzgerald & Assoc.)

In-process photo of the Light-field Directing Array (LDA) MEMS prototype designed by Lawrence Livermore National Laboratory. (Source: AMFitzgerald & Assoc.)

For the past several years, AMFitzgerald has been developing the fabrication process for a novel MEMS micro-mirror array designed by Dr. Robert Panas’s research group at LLNL, as shown in this video. The technology has been developed specifically to serve LIDAR, laser communications, and other demanding applications where existing MEMS mirror array technologies are insufficient. The novel design offers exceptional speed and tilt range, with three axes (tip-tilt-piston), feedback control, and 99% fill factor. The technology is available for license from the LLNL Industrial Partnerships Office.

At the upcoming MEMS & Sensors Technical Congress, on May 11, Dr. Carolyn D. White will present a case study on how she developed this complex prototype and leveraged AMFitzgerald’s ecosystem of partners to integrate specialty processes. Dr. Alissa Fitzgerald—founder and principle of AMFitzgerald leading the development of innovative MEMS and sensor solutions for specialty applications—will be giving a keynote address on “Next Generation MEMS Manufacturing” at 9:10am May 17 during The ConFab. Dr. Fitzgerald has unparalleled expertise in how to best design MEMS for different fab lines, and is a speaker not to be missed.


EUVL Masks may need to be Tool-Specific

Extreme Ultra-Violet Lithography (EUVL) keeps hurting my brain. Just when I can understand how it could be used in profitable commercial high-volume manufacturing (HVM) I hear something that seriously strains my brain. First it was the mirrors and mask in vacuum, then it was the resist and pellicle, then it was the source power and availability, and in each case scientists and engineers did amazing work and showed a way to HVM. Now we hear that EUVL might require fabs to park work-in-progress (WIP) lots of wafers behind a single critical tool with an idealistic 80% availability on a good day, and lots of downtime bad days. Horrors!

For “5nm-node” designs the maximum allowable edge placement-error (EPE) in patterning overlay is only 2nm. While the physics of ~13.5nm wavelength EUVL means that aberration in the reflecting mirrors appears as up to 3nm variation in the fidelity of projected patterns. This variation can be measured and compensated for at the physical mask level, but then each mask would only be good for one specific exposure tool. John Sturtevant—SPIE Fellow, and director of RET product development in the Design to Silicon Division at Mentor Graphics—briefly discussed this on February 26th during Nikon LithoVision held just before SPIE Advanced Lithography.

Sturtevant explained that the Zernike coefficients for EUV are inherently almost 1 order-of-magnitude higher than for DUV at 193nm wavelength, as detailed in the SemiMD article “Edge Placement Error Control in Multi-Patterning.” How the inherent physical sources of aberration must be tightened to avoid image distortion and contrast loss as they scale with wavelength was discussed by by Fenger et al. in 2013 in the article “Extreme ultraviolet lithography resist-based aberration metrology” (doi:10.1117/1.JMM.12.4.043001).


ASM’s Haukka ALD Award

Dr. Suvi Haukka, executive scientist at ASM International, located in Finland, was awarded the ALD Innovation prize at the ALD 2016 Ireland conference (Figure), as chosen by the conference chairs. Haukka has had a lifetime career in Atomic Layer Deposition (ALD), starting at Microchemistry Ltd. with ALD pioneer Dr. Tuomo Suntola in 1990, and now holding over 100 patents.

Conference co-chairs Simon Elliott, Tyndall National Institute of Ireland (left) and Jonas Sundqvist, Lund University of Sweden (right) acknowledge Suvi Haukka from ASM International N.V. (center) as recipient of the "ALD Innovation Prize" at the 16th International Conference on Atomic Layer Deposition (ALD 2016) held last month in Dublin, Ireland. (Source: ALD 2016)

Conference co-chairs Simon Elliott, Tyndall National Institute of Ireland (left) and Jonas Sundqvist, Lund University of Sweden (right) acknowledge Suvi Haukka from ASM International N.V. (center) as recipient of the “ALD Innovation Prize” at the 16th International Conference on Atomic Layer Deposition (ALD 2016) held last month in Dublin, Ireland. (Source: ALD 2016)

Since ASM bought Microchemistry in 1999, Haukka has worked on the manufacturability of ALD processes for the semiconductor industry. Today, ALD technology is essential for the high-volume manufacturing (HVM) of advanced ICs, with growing demand for the fabrication of nanoscale 3D devices such as finFETs and 3D-NAND Flash cells.

As reported by Riikka Puurunen in his ALD History Blog, Haukka joins a short list of technology luminaries who have been previous recipients of the prize:
* 2011 Roy Gordon (Harvard University),
* 2012 Markku Leskelä (University of Helsinki),
* 2013 Steven George (University of Colorado),
* 2014 Hyeongtag Jeon (Hanyang University), and
* 2015 Gregory Parsons (North Carolina State University).

More on the ALD 2016 conference can be read in the travel report blog.

[DISCLAIMER:  Ed Korczynski and Jonas Sundqvist also work for TECHCET CA, and were co-chairs of the 2016 Critical Materials Conference.]


Eloquent Executives Ecosystem Expositions


With dimensional scaling reaching economic limits, each company in the IC fab industry must rely upon trusted connections with customers and suppliers to know which way to go, and the only way to gain trusted connections is through attending live events. Fortunately, whether you are an executive, and engineer, or an investor, there is at least one must-attend event happening these days to keep you informed.

We should always start with SEMI (sponsor of SemiMD, personal friends for many years) who has always represented the gold standard for trade-shows, executive events, and manufacturing symposia around the world. I attended my first SEMICON/West in 1988, and have since attended excellent SEMICONs in Europe, Japan, Korea, China, and Singapore. This year’s SEMICON gathering in San Francisco will feature a nearly 50% increase in the number of technical sessions.

SEMI ran another excellent Advanced Semiconductor Manufacturing Conference (ASMC) in Albany this month, featuring keynotes by visionaries such as “Nanoscale III-V CMOS” by MIT Professor Jesus A. del Alamo. The panel discussion “Moore’s Law Wall vs. Moore’s Wallet, and where do we grow from here,” was moderated by industry veteran Paul Werbaneth, now with Intevac. It is clear that we will reach economic limits of scaling well before the physical limits.

Materials technology and supply-chain solutions to extend economic limits were discussed by Intel’s VP of Technology and Manufacturing Tim Hendry in a keynote at the Critical Materials Conference (CMC) held this year in Oregon in early May, as produced by Techcet CA (I am also an analyst with Techcet and co-chair of this event, while Solid State Technology was a media sponsor). David Thompson, Senior Director, Center of Excellence in Chemistry, Applied Materials showed that despite the inherent “Agony in New Material Introductions – minimizing and correlating variabilities” is possible with improved collaboration throughout the supply-chain.

The Imec Technology Forum in Brussells this month (Solid State Technology was a media sponsor) could best be described with Lake Wobegone hyperbole that all the women were strong, the men were good-looking, and everyone was above average. The big news is imec acquiring iMinds for greater synergies when integrating the latter’s algorithms with imec-ecosystem hardware for application-specific solutions. Gary Patton, now CTO and SVP of Global R&D for GLOBALFOUNDRIES, reminded everyone at ITF of the inherent speed constraints of the copper wires and low-k dielectrics needed to connect IC transistors, “As I’ve often said, It’s like you have a Ferrari but you’re towing a boat if you don’t address the interconnect delay issues.” Regardless, Patton confidently declares that, “We will continue to provide value to our customers to be able to create new products, and we will innovate in ways other than simple scaling.”

At ITF, a video was shown of imec president Luc van den Hove interviewing Gordon Moore at his beachfront home in Hawaii. Moore has always been humble and claims no special ability to forecast trends. “It would not surprise me if we reached the end of scaling in the next decade,” said Moore. “I missed the importance of the PC, and I missed the importance of the internet. Predicting the future is a difficult job and I leave it to someone else.”

Wally Rhines seemed able to predict the future when he eloquent expounded upon Moore’s Law as a special-case learning-curve in his presentation at ITF. Rhines will provide one of the keynote addresses at the ConFab in Las Vegas this year (Solid State Technology’s home event, co-sponsored by SEMI and by IEEE-CPMT). Executives from the global industry will gather to hear insights and analysis on the challenges facing all companies in the ecosystem, as we search for profitable pathways in a more complex landscape.


Trefonas Earns 2016 Perkin Medal

The Society of Chemical Industry (SCI), America Group, announced on May 5, 2016 that Peter Trefonas, Ph.D., corporate fellow in Electronic Materials at Dow Chemical Co (NYSE:DOW), has won the 2016 SCI Perkin Medal. This honor recognizes Trefonas’ contributions in the development of chemicals that enable microlithography for the fabrication of microelectronic circuits. Trefonas will receive the medal at a dinner in his honor on Tuesday, September 13, 2016, at the Hilton Penn’s Landing Hotel in Philadelphia.

TrefonasTrefonas made major contributions to the development of many successful products which are used in the production of integrated circuits spanning device design generations from 2 microns to 14 nanometers. These include photoresists, antireflectant coatings, underlayers, developers, and ancillary products. At the most recent SPIE Advanced Lithography conference he was part of a team that presented on the use of a resolution extension material, “Chemical trimming overcoat: an enhancing composition and process for 193nm lithography.”

He is an inventor on 61 US patents, has over 25 additional published active U.S. patent applications, is an author of 99 journal and technical publications, and is a recent recipient of both the 2014 ACS Heroes of Chemistry Award and the 2014 SPIE Willson Award. His research career began at Monsanto, and moved via acquisitions by Shipley, Rohm&Haas, and Dow.


RFID Playing Cards “Best Product” at Printed Electronics Europe

Cartamundi, imec and Holst Centre (set up by imec and TNO) recently won the Best Product Award at Printed Electronics Europe for their ultra-thin plastic RFID technology integrated into Cartamundi’s playing cards. In each card, the RFID chip has a unique code that communicates wirelessly to an RFID reader, giving the cards in the game a unique digital identity. The jury recognized the potential of this technology to enhance printed electronics applications for the Internet-of-Things (IoT), as well as being a gamechanger <RIMSHOT> for the gaming industry.

Cartamundi-imec_RFID_PrintedChris Van Doorslaer, CEO of Cartamundi, said, “The new technology will connect traditional game play with electronic devices like smartphones and tablets. As Cartamundi is committed to creating products that connect families and friends of every generation to enhance the valuable quality time they share during the day, this technology is a real enabler.” Imec and Cartamundi engineers will now explore up-scaling of the technology using a foundry production model.

“This is a thrilling development to demonstrate our TOLAE electronic technology integrated in the product of a partner company. TOLAE stands for Thin, Oxide and Large-Area Electronics”, stated Paul Heremans, department director of thin-film electronics at imec and technology director at the Holst Centre. “Our prototype thin-film RFID is thinner than paper—so thin that it can be invisibly embedded in paper products, such as playing cards. This key enabling technology will bring the cards and traditional games of our customer in direct connection with the Cloud. This achievement also opens up new applications in the IoT domain that we are exploring, to bring more data and possibilities to applications such as smart packaging, security paper, and maybe even banknotes.”


Omhi kept us Ultra-Clean

OhmiSadly, I just recently learned from the UCPSS 2016 website that Ohmi-sensei—Professor Doctor Tadahiro Ohmi—passed away in Sendai on 21 February 2016. As the guru of ultra-clean technology, he established the global Ultra Clean Society in 1988, founded the International Symposium of Semiconductor Manufacturing (ISSM) in 1992, served as program committee member of the UCPSS between 1992 and 2006, and was an IEEE Fellow. Ohmi was a Professor of New Industry Creation Hatchery Center at Tohoku University, after serving as a Professor at the Electronic Engineering Department, School of Engineering at Tohoku U.

Ohmi was most famous for asserting that IC manufacturing yield could be 100% if only every tool and tube in the fab were built with ultra-clean surfaces, and if all direct-materials and fluids flowing in the fab were ultra-clean. In the 1980s when IC designs and fab processes were relatively simple and HVM yields were in the 30-60% range, huge improvements came from removing “random” particles from dirty surfaces. Soon enough by the mid-1990s  “clean enough” was found to be the pragmatic response to the experience of diminishing returns after yields were in the 90% range. Most famously for posterity, in 1993 Ohmi edited “Ultraclean Technology Handbook: Ultrapure Water, Vol.1”.

I first met him when UltraClean Technology, Inc. (UCTT) was founded in California in 1996 to weld ultra-clean steel from parent company Mitsubishi in a Class-1 cleanroom, and he was the genius bringing his vision of a better world to the rest of us. However, eventually UCTT separated from Mitsubishi and added Class-100 and Class-1000 assembly areas to provide “clean enough” technology…heresy to the Guru of ultra-clean; I never met him again when I worked for the company as a product manager in 2004.

As covered by EETimes in 2002, Ohmi could clearly see that something new was going to be needed in fab technology, but his vision for a way forward was an unrealizable dream:

Ohmi said his comprehensive process, from design through chip making, would create devices with 10 times better performance than today’s chips. At the same time, he said, it would squeeze design and production time to 1/40, clean room space to 1/5 and production cost to 1/10 of what’s now required.

Throughout his career he continued to look for breakthroughs to enable new generations of semiconductor manufacturing technology, recently supervising a project to develop a “next-generation flat panel display.”

An extraordinarily prolific inventor, his name is on an astonishing 592 issued US patents, based on 795 US applications filed, the most recent on December 21st of last year.


SAQP Specs for 7nm finFETs

As discussed in my last Ed’s Threads, lithography has become patterning as evidenced by first use of Self-Aligned Quadruple Patterning (SAQP) in High Volume Manufacturing (HVM) of memory chips. Meanwhile, industry R&D hub imec has been investigating use of SAQP for “7nm” and “5nm” node finFET HVM, as reported as SPIE-AL this year in Paper 9782-12.
The specifications for pitches ranging from 18 to 24 nanometers are as follow:

  • 7.0nm Critical Dimension (CD) after etch,
  • 0.5nm (3sigma) CD uniformity (CDU), and
  • <1nm Line-Width and Line-End Roughness (LWR and LER) assuming 10% of CD.

“Pitch walk”—variation in final pitch after multi-patterning—results in different line widths, and can result in subsequent excessive etch variation due to non-uniform loading effects. To keep the pitch walk in SAQP at acceptable levels for the 7nm node, the core-1 CDU has to be 0.5nm 3sigma and 0.8nm range after both litho and etch. In other presentations at SPIE-AL this year, the best LER after litho was ~4nm, improving to ~2nm after PEALD smoothing of sidewalls, but still double the desired spec.

The team at imec developed a SAQP flow using amorphous-Carbon (aC) and amorphous-Silicon (aSi) as the cores, and low-temperature Plasma-Enhanced Atomic-Layer Deposition (PEALD) of SiO2 for both sets of spacers. Bilayer DARC (SiOC) and BARC were used for reflectivity control. Compared to SAQP schemes where the mandrels are only aSi, imec claims that this approach saves 20% in cost due to the use of aC core and the elimination of etch-stopping-layers.